Bus Clock Handover Circuit to Prevent Missing or Spurious Pulses
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Solution Overview
Problem
In portable equipment, the need for a common clock signal for multiple bus circuits increases power consumption and can lead to driving conflicts, especially when different bus circuits require different clock signals, resulting in spurious or missing clock pulses that disrupt operation.
Innovation Solution
The apparatus allows for handover of clock control between different bus circuits, ensuring that the clock conductor is never floating and preventing conflicting driving conditions by adjusting the number of clock cycles based on predetermined intervals and ratios, enabling the use of push-pull driving circuits instead of wired logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common clock circuit with push-pull driver is used for all bus circuits, then clock signal distribution is simplified, but power consumption significantly increases
Solution Approach 1:
The patent divides the clock signal generation into separate segments, with each bus circuit having its own clock source that can independently drive the clock conductor. This eliminates the need for a single common clock circuit that would consume excessive power, while still providing synchronized clock signals to all circuits through the shared clock conductor.
Solution Approach 2:
The patent implements dynamic clock handover mechanisms where different bus circuits can take control of the clock conductor at different times based on their operational needs. This dynamic allocation allows circuits to power down their clock sources when not needed, significantly reducing overall power consumption while maintaining clock signal availability when required.
2Use of energy by moving object
If different bus circuits each drive the clock signal independently, then power consumption is reduced, but driving conflicts arise on the clock conductor
Solution Approach 1:
The patent introduces arbitration mechanisms and control circuits that act as intermediaries between multiple clock sources and the shared clock conductor. These intermediaries coordinate the clock driving activities, ensuring that only one circuit drives the clock conductor at any given time, thereby preventing driving conflicts while maintaining power efficiency.
Solution Approach 2:
The patent implements preliminary arbitration and handover protocols that determine clock driving rights before actual clock signal generation begins. This preliminary coordination ensures smooth transitions between different clock sources without causing conflicts or signal instability, maintaining reliable clock operation while allowing power-efficient independent clock sources.
3Adaptability or versatility
If wired OR logic is used for clock generation, then multiple bus circuits can share the clock conductor, but circuit speed slows down and power supply consumption increases
Solution Approach 1:
The patent replaces the passive wired OR logic mechanism with active push-pull driver circuits that can rapidly switch the clock conductor between high and low states. This substitution eliminates the speed limitations and power consumption issues inherent in wired OR logic, while maintaining the ability of multiple bus circuits to share the clock conductor through coordinated driving.
Data Source
AI summary
Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period following the start of execution of the handover command and to continue driving the clock conductor (10a) to the predetermined voltage level for a first time-interval. The clock conductor (10a) is driven to the predetermined voltage level with the driver circuit of the second circuit after a second time interval following the start of execution of the handover command until a third time interval has elapsed following the end of the second time interval. Subsequently the clock conductor (10a) is driven under control of the clock circuit (140) of the second circuit (14). The first time interval contains a first integer number P1 of periods of a first clock signal of the first circuit and the second and third time interval contain a second and third integer number P2, P3 of periods of a second clock signal of the second circuit, a duration corresponding to the second integer number P2 equaling at least a pulse duration of the first clock signal, a duration corresponding to the first integer number P1 equaling at least a duration corresponding to the second integer number P2 plus one, a duration corresponding to the second plus third integer P2, P3 equaling at least a duration corresponding to the first number P1 plus one.