Bus-Based Clock to Out Path Optimization in FPGAs
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Solution Overview
Problem
Conventional placing and routing software struggles to efficiently satisfy the relative clock to out vs. clock out timing requirements in programmable logic devices, such as FPGAs, as it often fails to converge on optimal placement and routing choices that meet the desired delay differences between these paths.
Innovation Solution
A novel placing and routing algorithm that not only minimizes the clock to out path delay but also adjusts the clock out path delay to satisfy the maximum allowed difference between the two, using individual delay offsets and a bus-based timing optimization technique to ensure compliance with both minimum and maximum delay differences across multiple paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional placing and routing software is used to minimize clock to out path delay, then the clock to out timing requirement is improved, but the clock out path delay may not satisfy the maximum allowed difference requirement
Solution Approach 1:
The patent segments the timing optimization process into two independent phases: first optimizing the clock to out path delay, then separately optimizing the clock out path delay. This segmentation allows each path to be optimized independently while satisfying the maximum difference requirement between them, resolving the contradiction between minimizing clock to out delay and ensuring timing requirement satisfaction.
Solution Approach 2:
The patent performs preliminary optimization of the clock to out path delay first, then uses the result as a baseline for the subsequent clock out path optimization. This preliminary action ensures that the more critical clock to out timing is satisfied before addressing the clock out path, thereby resolving the contradiction between the two timing requirements.
2Adaptability or versatility
If placing and routing flexibility is increased to accommodate various paths, then device adaptability is improved, but timing convergence becomes more difficult
Solution Approach 1:
The patent segments the timing optimization into two independent phases, which simplifies the convergence process despite maintaining placing and routing flexibility. By handling clock to out and clock out path optimization separately, the algorithm avoids the complexity of simultaneously satisfying both timing requirements while maintaining full routing flexibility.
Solution Approach 2:
The patent changes the optimization parameters sequentially: first optimizing for clock to out delay, then optimizing for clock out delay while maintaining the results from the first phase. This parameter change approach allows the algorithm to maintain routing flexibility while reducing timing convergence complexity through staged optimization.
Data Source
AI summary
A place and route technique is provided for a programmable logic device to optimize a delay difference between a bus including a plurality of clock to out paths and a corresponding clock out path.