Bus Connection Circuit Mirror Area Detection for 1-Cycle Transfer
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Solution Overview
Problem
Existing bus transfer techniques in semiconductor integrated circuits face inefficiencies when mixing direct and non-direct transfers, requiring additional settings for the memory controller, which reduces bus transfer efficiency.
Innovation Solution
A bus connection circuit with a mirror area access detecting circuit and processing circuit that detects bus master accesses to a mirror area and executes preset processing, allowing 1-cycle transfers without additional memory controller settings by using a direct transfer write strobe signal to differentiate between direct and non-direct transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If 1-cycle direct transfer is implemented between bus slaves, then transfer speed is improved, but device complexity increases due to additional memory controller settings
Solution Approach 1:
The bus connection circuit automatically detects mirror area accesses and determines whether 1-cycle transfer or 2-cycle transfer should be performed without requiring external control signals or memory controller settings. The circuit serves itself by using the address signal patterns to automatically select the appropriate transfer mode, eliminating the need for complex external configuration.
Solution Approach 2:
The invention changes the address signal parameters by allocating specific address ranges (mirror areas) that encode transfer mode information. By embedding transfer mode indicators within the address signal itself rather than using separate control signals, the system achieves mode switching without increasing external control complexity.
2Adaptability or versatility
If memory controller settings are changed for each transfer type, then transfer flexibility is improved, but bus transfer efficiency deteriorates due to overhead
Solution Approach 1:
The bus connection circuit autonomously determines the appropriate transfer mode by detecting mirror area accesses in the address signal, eliminating the need for external memory controller configuration. This self-determination mechanism maintains transfer flexibility while removing the overhead associated with external setting changes.
Solution Approach 2:
The system pre-allocates mirror area address ranges that encode transfer mode information before transfers occur. This preliminary encoding of transfer mode indicators in the address space allows the bus connection circuit to immediately determine the correct transfer mode without requiring real-time configuration or setting changes.
3Speed
If 1-cycle transfer is used without mirror area detection, then transfer speed is improved, but reliability deteriorates due to inability to handle mixed transfer types
Solution Approach 1:
The bus connection circuit acts as an intermediary between the bus master and bus slaves, intercepting address signals and detecting mirror area accesses. Based on this detection, the circuit automatically selects the appropriate transfer mode (1-cycle or 2-cycle), ensuring reliable operation for mixed transfer types while maintaining high speed performance.
Solution Approach 2:
The invention uses address signal parameter changes (mirror area patterns) to encode transfer mode information. By decoding these embedded parameters, the bus connection circuit reliably determines whether to execute 1-cycle or 2-cycle transfers, ensuring correct operation without requiring external control or sacrificing transfer speed.
Data Source
AI summary
A bus connection circuit connects a bus master and a plurality of bus slaves. The bus connection circuit includes a mirror area access detecting circuit and a processing circuit. The mirror area access detecting circuit detects that the bus master accesses a mirror area of a first bus slave of the plurality of bus slaves, and output a detection signal based on a detection result. The processing circuit executes processing preset in correspondence to the detection result, to an area or data as an access object, based on the detection result.