Bus Control Circuit Arbitration for Single-Queue Packet Output
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Solution Overview
Problem
Existing bus control circuits are not optimized for scenarios where a packet is present only in one of the input queues, leading to slow packet output speed.
Innovation Solution
A bus control circuit design that includes multiple queues, first arbitration circuits, buffers, and a second arbitration circuit, which use a First in, First out (FIFO) basis and the Least Recently Used (LRU) method to arbitrate and manage arbitration participation signals, ensuring efficient packet output by prioritizing the oldest signals and optimizing packet transfer across multiple virtual channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional bus control circuit is used, then the structure is simple, but the packet output speed is slow when data is stored in only one queue
Solution Approach 1:
The arbitration circuit is divided into multiple first arbitration circuits that each handle a subset of queues, and a second arbitration circuit that handles the final selection. This segmentation allows parallel processing of arbitration requests and improves packet output speed when data is concentrated in fewer queues.
Solution Approach 2:
Buffers are introduced as intermediary elements between the first arbitration circuits and the second arbitration circuit. The buffers store arbitration participation signals and enable asynchronous operation, allowing the arbitration process to proceed without blocking the data transfer path.
2Productivity
If multiple arbitration circuits are added to improve packet output speed, then the throughput increases, but the device complexity increases
Solution Approach 1:
The arbitration function is segmented into multiple first arbitration circuits that operate in parallel, each handling a subset of queues. This allows the system to process multiple arbitration requests simultaneously, increasing throughput without requiring a complete redesign of the arbitration logic.
Solution Approach 2:
The arbitration process is extended to a second dimension by introducing a second arbitration circuit that receives inputs from multiple buffers and makes the final selection. This hierarchical structure enables efficient arbitration across multiple queues while maintaining manageable complexity through modular design.
3Speed
If the bus control circuit is optimized for single-queue data storage, then the packet output speed improves, but the cache coherency may be compromised
Solution Approach 1:
The arbitration circuits continuously monitor the status of queues and adjust their arbitration decisions based on feedback about data availability. This feedback mechanism ensures that high-speed data transfer from single queues does not compromise cache coherency by selectively arbitrating based on actual data presence while maintaining coherence protocols.
Solution Approach 2:
The arbitration logic dynamically changes its behavior based on the distribution of data across queues. When data is concentrated in fewer queues, the arbitration circuit prioritizes those queues to maximize transfer speed. When data is distributed more evenly, the arbitration maintains fairness to preserve cache coherency, thus adapting parameters to balance performance and reliability.
Data Source
AI summary
A bus control circuit includes: a plurality of queues that each include a plurality of entries for storing data, a first read pointer, and a check pointer set to indicate a same entry as an entry indicated by the first read pointer, and each store data on a First in, First out basis; a plurality of first arbitration circuits that receive, in a divided manner, arbitration participation signals from the plurality of queues, each arbitrate the received plurality of arbitration participation signals, and each output one of the plurality of arbitration participation signals; a plurality of buffers that each store, on the First in, First out basis, the arbitration participation signals output from the respective first arbitration circuits; and a second arbitration circuit that arbitrates the arbitration participation signals output from the plurality of buffers and outputs an arbitration result signal corresponding to one of the plurality of queues.