Bus Control Circuit for Dynamic Urgent-Access Priority
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Solution Overview
Problem
In semiconductor devices with multiple bus masters, urgent processing may not be completed within a predetermined time due to limited bandwidth or lowered priority, leading to potential delays in critical operations.
Innovation Solution
A semiconductor device with a bus control circuit that includes priority determination circuits to dynamically adjust priority levels, allocating high priority to urgent requests and reducing priority for other masters, thereby enhancing bandwidth allocation and prioritization during emergency situations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If priority arbitration is performed based on QoS information in a bus system with multiple masters, then normal processing can be managed according to priority levels, but urgent processing may still experience bandwidth limitation and priority reduction causing delays
Solution Approach 1:
The priority determination circuit dynamically adjusts priority levels based on the type of access request. When urgent access is detected, the circuit changes the priority level signal to allocate high priority to the corresponding master and low priority to other masters, making the arbitration mechanism adaptive rather than static
Solution Approach 2:
The patent applies different priority treatment to different masters based on their access types. The priority determination circuit identifies the specific master making urgent access and applies high priority only to that master while assigning low priority to other masters, creating localized quality differentiation
2Productivity
If bandwidth is allocated to multiple masters simultaneously, then normal operations can proceed in parallel, but urgent processing from any single master may be delayed due to shared bandwidth limitations
Solution Approach 1:
The bus control circuit dynamically reallocates bandwidth based on priority level signals from the priority determination circuit. When urgent access is detected, the circuit changes bandwidth allocation from shared to dedicated for the urgent master, making the resource distribution adaptive
3Stability of the object's composition
If priority levels are maintained at normal levels for all masters, then system stability is preserved, but urgent processing cannot receive the necessary bandwidth allocation to complete within predetermined time
Solution Approach 1:
The priority determination circuit dynamically changes priority level signals from normal levels to high/low levels when urgent access is detected, allowing the system to transition from stable normal operation to dynamic emergency response as needed
Data Source
AI summary
A semiconductor device includes a bus control circuit that controls access to a slave shared by a plurality of masters. The bus control circuit includes a plurality of priority determination circuits corresponding to the plurality of masters. The priority determination circuit is configured to, when receiving an urgent access from a corresponding master, change a priority level signal included in an access request from the corresponding master to allocate a high priority level for emergency and allocate a low priority level to a master other than the corresponding master.