Bus Controller Descriptor-Based Data Transfer
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Solution Overview
Problem
Current computer system architectures face limitations in data transfer rates to I/O devices, particularly due to the continuous involvement of processor cores in direct memory access operations, which can lead to performance degradation and bottlenecks.
Innovation Solution
A data processing apparatus with a shared processor cache and a bus controller that initiates direct memory access by receiving a descriptor from a processor core, allowing data transfer from the shared processor cache to I/O devices without continuous processor core involvement, leveraging a bus unit for high-speed data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processor cores continuously participate in direct memory access operations, then data transfer control is maintained, but system performance degrades due to processor involvement
Solution Approach 1:
The patent extracts the data transfer control function from the processor core and transfers it to the bus controller. The processor core only needs to write a descriptor to the shared cache to initiate a transfer, after which the bus controller autonomously manages the entire data transfer process between the shared cache and I/O devices, eliminating the performance degradation caused by continuous processor involvement.
Solution Approach 2:
The bus controller serves as an intermediary between the processor core and the data transfer operation. It receives descriptors from the processor core, interprets them, and autonomously executes the data transfer between the shared cache and I/O devices, allowing the processor to continue executing other tasks without waiting for data transfers to complete.
2Productivity
If data transfer rate to I/O devices is increased, then system throughput improves, but bandwidth constraints and latency increase
Solution Approach 1:
Data is pre-loaded into the shared cache before being transferred to I/O devices. The bus controller can initiate data transfers from the shared cache without waiting for data to be fetched from main memory during the actual transfer operation, reducing latency and enabling higher data transfer rates by having data ready in advance.
Solution Approach 2:
The shared cache maintains continuous data availability for I/O devices by keeping data in the cache while the bus controller manages transfers. This eliminates idle time and maintains continuous useful action during data transfer operations, improving both throughput and reducing effective latency.
3Speed
If processor cache is used for data storage, then access speed improves, but cache coherency management becomes more complex
Solution Approach 1:
The patent extracts data transfer management from the processor core and assigns it to the bus controller, which simplifies cache coherency management. The processor core only writes descriptors to indicate transfer intentions, while the bus controller autonomously handles the actual data movement, reducing the complexity of cache coherency protocols that the processor must manage.
Data Source
AI summary
A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.