Bus Controller and FIFO Buffer for PLD Communication
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Solution Overview
Problem
The increasing complexity of processing systems, particularly in multimedia and video designs, leads to prohibitively long simulation times and communication bottlenecks between standard computation devices and hardware emulators in programmable logic devices, hindering the testing and verification process.
Innovation Solution
A method and apparatus for improved communication between a processor and hardware blocks in a programmable logic device, utilizing a bus controller, FIFO buffers, a processing engine, address decoder, strobe generator, shared memory, and memory controller to facilitate efficient data transfer and access arbitration among hardware blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of test vectors are applied to a software simulation of the design, then testing coverage is improved, but simulation time becomes prohibitively long
Solution Approach 1:
The patent introduces hardware emulators as an intermediary between the test engine and the design under test. These emulators provide a more efficient execution environment for hardware portions of the design, allowing parallel processing and significantly reducing simulation time while maintaining comprehensive test coverage. The hardware emulator acts as a mediator that bridges software-based test control with accelerated hardware execution.
Solution Approach 2:
The patent divides the processing system into distinct software and hardware components. The test engine running on a standard computation device handles software-based testing, while hardware emulators handle hardware-based testing. This segmentation allows each component to operate in its optimal environment, with the hardware portion executing test vectors in parallel, thereby reducing overall simulation time while maintaining comprehensive coverage.
2Reliability
If hardware emulators are used for more accurate and efficient simulation, then simulation accuracy is improved, but communication bottlenecks between the test engine and hardware emulators increase
Solution Approach 1:
The patent extends the communication interface beyond traditional single-dimensional data transfer by implementing a multi-dimensional communication architecture. This includes direct memory access (DMA) capabilities, interrupt mechanisms, and synchronized data transfer protocols that operate across multiple communication dimensions simultaneously. This allows the test engine and hardware emulators to exchange large volumes of data efficiently without creating bottlenecks.
3Productivity
If the interface between the standard computation device and hardware emulators is enhanced, then communication efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal communication interface that handles multiple functions through a single standardized architecture. The interface supports data transfer, control signal exchange, interrupt handling, and synchronization protocols all through one unified communication pathway. This multi-functional design reduces the need for separate dedicated interfaces for each communication need, thereby improving efficiency without proportionally increasing complexity.
Data Source
AI summary
Method and apparatus for communication between hardware blocks configured in a programmable logic device (PLD) and a computation device external to the PLD is described. A bus controller is provided for receiving words from the computation device. Each of the words includes an address component and a data component. A first-in-first-out buffer (FIFO) is configured for communication with the bus controller to store the words. A processing engine is provided having a memory space associated with the hardware blocks and being configured to receive a word at a top of the FIFO. An address decoder is provided for decoding the address component of the word at the top of the FIFO to obtain an address of a memory location in the memory space. A strobe generator is provided for coupling a strobe signal to the processing engine. The strobe signal is configured to store the word in the memory location.