Bus Controller Load Balancing for NoC Power Reduction
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Solution Overview
Problem
Conventional network-on-chip (NoC) technologies face inefficiencies in data transfer over semiconductor chip communications buses, leading to imbalanced traffic flow rates and increased power dissipation and chip area requirements, especially as the demand for broader bandwidths grows without raising operating frequencies.
Innovation Solution
A bus controller system that includes a route load detector, candidate route extraction circuit, selection rule storage, route determining circuit, header building circuit, and data communication circuit to manage and distribute data loads uniformly across multiple routes, reducing operating frequencies and power dissipation while maintaining high bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is performed over communication buses in conventional NoC, then data can be transmitted between functional modules, but traffic flow rates become imbalanced and power dissipation increases
Solution Approach 1:
The patent implements dynamic route selection where the route determining circuit selects different routes based on real-time load conditions detected by the route load detector. This dynamic adaptation allows the system to balance traffic flow rates across multiple routes, preventing any single route from becoming overloaded and thereby reducing power dissipation while maintaining high data transfer efficiency.
Solution Approach 2:
The system changes the parameter of route selection based on detected load conditions. By monitoring traffic flow rates on different routes and selecting routes with lower loads, the system optimizes power dissipation and transfer efficiency. The route determining circuit uses the detected load parameters to make intelligent routing decisions that balance the network traffic.
2Speed
If operating frequency is increased to achieve broader bandwidth, then data transfer speed improves, but power dissipation and chip area requirements increase
Solution Approach 1:
The patent divides the data transfer function into multiple parallel routes, allowing data to be segmented and transmitted simultaneously across different paths. This segmentation enables broader effective bandwidth without increasing the operating frequency of individual routes, thereby avoiding the associated power dissipation and chip area increases that would result from frequency scaling.
Solution Approach 2:
Instead of increasing bandwidth by increasing frequency (one dimension), the patent introduces the dimension of multiple parallel routes. By distributing data across multiple spatial paths, the system achieves broader effective bandwidth while maintaining lower operating frequencies, thus reducing power dissipation and chip area requirements.
3Productivity
If multiple routes are used to increase bandwidth, then data transfer capacity improves, but route selection complexity increases
Solution Approach 1:
The route determining circuit autonomously selects routes based on load information detected by the route load detector without requiring external control or complex centralized management. This self-service mechanism simplifies the overall system architecture by distributing the route selection intelligence to the endpoints, reducing the complexity of route management while enabling effective use of multiple routes for increased bandwidth.
4Ease of operation
If transmitting-end modules independently select routes, then decentralization is achieved, but traffic flow imbalance persists
Solution Approach 1:
The patent implements a feedback mechanism where the route load detector continuously monitors traffic flow rates on different routes and provides this information to the route determining circuit. This feedback loop enables the transmitting-end module to make informed route selection decisions that consider overall network conditions, thereby achieving both independent operation and balanced traffic flow distribution across multiple routes.
Data Source
AI summary
In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.