Bus Controller Multiplexer for Expandable Computing Systems

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-end computing systems with optional processors often render I/O or expansion slots non-functional when the corresponding processor or bus controller is not installed, limiting system expandability and utilization.

Innovation Solution

A computing system architecture that includes a first bus controller, a second bus controller, and a 2-to-1 multiplexer, where the multiplexer selects between lanes from the first and second bus controllers based on the presence of the second bus controller, allowing the system component to interact with either controller, ensuring functionality regardless of the optional processor's installation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If an optional processor or bus controller is not installed in the computing system, then system cost and complexity are reduced, but the I/O or expansion slots become non-functional

Engineering Contradiction:
Improvesystem expandabilityVSAvoidslot functionality
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The multiplexer enables the I/O slot to be universally accessible by either the first bus controller or the second bus controller. The slot is designed to be agnostic to which controller is present, allowing the same slot to function whether the system uses only the first controller, only the second controller, or both controllers interchangeably.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The multiplexer acts as an intermediary device between the two bus controllers and the I/O slot. It mediates the connection by selectively routing signals from either controller to the slot based on which controller is currently active, thereby ensuring continuous slot functionality regardless of controller configuration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a multiplexer is added to enable slot functionality with optional processors, then system expandability is improved, but device complexity increases

Engineering Contradiction:
Improveslot accessibilityVSAvoidcontroller architecture
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The multiplexer is configured to automatically detect which bus controller is present and selectively connect the I/O slot to the appropriate controller without requiring manual intervention or complex control logic. The system self-adjusts based on the presence or absence of the optional processor or controller.

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If the system is designed to support optional processors, then system customization and cost-effectiveness are improved, but system utilization and flexibility deteriorate

Engineering Contradiction:
Improvesystem customizationVSAvoidsystem utilization
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The I/O slot is designed with universal compatibility to work with either the first bus controller or the second bus controller. This universality ensures that the slot remains functional and useful across different system configurations, maximizing system utilization regardless of which controller is present.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3111334B1Computing system control
Publication Date: 2020.01.22 HEWLETT PACKARD DEVELOPMENT COMPANY LP
  • EP3111334B1 patent drawingFigure 1
  • EP3111334B1 patent drawingFigure 2
  • EP3111334B1 patent drawingFigure 3A

AI summary

In one example in accordance with the present disclosure, a computing system is provided. The computing system includes a first bus controller to control X bus lanes, a second bus controller to control Y bus lanes, a 2-to-1 X lane multiplexer, and a Y lane system component, where Y > X > 0. X lanes from the first bus controller are coupled to the 2-to-1 X lane multiplexer. X lanes from the second bus controller are coupled to the 2-to-1 X lane multiplexer, and Y - X lanes from the second bus controller are coupled directly to the Y lane system component. In addition, X lanes from the 2-to-1 X lane multiplexer are coupled to the Y lane system component.