Bus Data Transfer Simulation Using Anticipated Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data processing apparatus simulation techniques face a trade-off between accuracy and speed, with simplistic models providing limited information quickly but being inaccurate, and complex models being slow and accurate, while also requiring detailed modeling of bus arbitration and signal generation.
Innovation Solution
A method that generates anticipated timing information assuming exclusive bus access for most data transfers, with revised timing information generated using bus status information only when concurrent transfers are anticipated, optimizing for speed and accuracy by using efficient modeling for exclusive access scenarios and detailed modeling for concurrent scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complex model is used to accurately model the timing relationship between component units, then measurement precision of timing information is improved, but execution time increases significantly
Solution Approach 1:
The simulation process is segmented into two distinct phases: a rapid anticipated timing information generation phase that assumes exclusive bus access, and a corrective phase that only executes when concurrent transfers are detected. This segmentation allows the system to benefit from both fast simple modeling and accurate complex modeling without always incurring the cost of complex modeling.
Solution Approach 2:
The system applies partial action by only executing the complex bus status information modeling when necessary (when concurrent transfers are anticipated), rather than always executing it. This partial application of complex modeling maintains accuracy where needed while avoiding unnecessary computational overhead in exclusive access scenarios.
2Productivity
If a simplistic model is used to simulate data transfer functionality, then execution speed is improved, but measurement precision of timing information deteriorates
Solution Approach 1:
The system performs preliminary action by first generating anticipated timing information using simple exclusive access assumptions before checking for potential conflicts. This preliminary fast modeling provides a baseline that is then verified or corrected only when necessary, maintaining high speed for the majority of cases while ensuring accuracy when needed.
Solution Approach 2:
The system uses feedback from comparing anticipated timing information against actual bus status to determine whether corrections are needed. This feedback mechanism allows the simple model to serve as the default while automatically switching to complex modeling only when the simple model proves inaccurate, thus maintaining both speed and precision.
3Measurement precision
If detailed modeling of bus arbitration logic and signal generation is implemented, then measurement precision of timing information is improved, but device complexity increases
Solution Approach 1:
The system applies local quality by implementing detailed bus status information modeling only in the specific local context where concurrent transfers occur, rather than throughout the entire simulation framework. The complex arbitration logic is localized to only those scenarios where it is actually needed, keeping the overall system simple while maintaining precision where required.
Data Source
AI summary
Simulation of the operation of a data processing apparatus having a number of master logic units and slave logic units coupled via a bus is provided. The data processing apparatus performs data transfers between the master logic units and the slave logic units over the bus. Anticipated timing information for each successive data transfer over the bus is generated by assuming that each successive data transfer can occur with exclusive access to the bus, determining whether the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, and in the event that the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, generating revised timing information for those data transfers, the revised timing information being generated using bus status information until those data transfers have been completed.