Bus-Decoding SoC Wake-Up Control for Low-Power Monitoring Nodes
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Solution Overview
Problem
In environmental monitoring systems, especially those using two-wire fire buses, there is a need to reduce energy consumption and processing capability requirements of microprocessor cores due to the increasing number of nodes, while maintaining effective data communication and processing.
Innovation Solution
A system-on-chip with a hardware decoder that decodes signal frames from an external bus, wakes up the microprocessor core only when necessary, and allows it to perform operations specified in the signal frame, reducing energy consumption and processing demands by using a hardware decoder independent of the microprocessor core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the microprocessor core continuously monitors the GPIO port to detect signals, then the system can respond to external commands in real-time, but the energy consumption increases and processing capability requirements rise
Solution Approach 1:
The system divides the monitoring function into two parts: the hardware decoder continuously monitors the bus and detects signal frames, while the microprocessor core only wakes up when needed to process commands. This segmentation allows the microprocessor to sleep most of the time, reducing energy consumption while maintaining real-time responsiveness through the hardware decoder's continuous monitoring capability.
Solution Approach 2:
The hardware decoder autonomously performs signal detection, frame reception, address matching, and wake-up triggering without requiring the microprocessor to be active. The decoder serves itself by handling the continuous monitoring task, freeing the microprocessor to enter low-power sleep mode while ensuring the system still responds to external commands in real-time.
2Ease of manufacture
If low specification components are used within node devices, then the overall system cost is reduced, but the processing capability requirements of the microprocessor core increase
Solution Approach 1:
The hardware decoder acts as an intermediary component between the external bus and the microprocessor core. It handles the complex tasks of signal frame reception, decoding, address matching, and wake-up triggering, allowing the use of simpler, lower-cost microprocessors that would otherwise be insufficient for handling these processing requirements.
Solution Approach 2:
The patent replaces software-based signal monitoring and decoding (which would require high-capability microprocessors) with a hardware-based decoder circuit. This substitution of hardware for software processing enables the use of low-specification, cost-effective microprocessors while maintaining full signal processing capability.
3Adaptability or versatility
If the number of nodes in the system increases, then the system coverage and functionality improve, but the energy consumption of each device becomes a more urgent issue
Solution Approach 1:
The microprocessor core operates in periodic cycles, alternating between sleep mode (low energy consumption) and active mode (processing commands). The hardware decoder enables this periodic operation by continuously monitoring for wake-up signals and triggering the microprocessor only when necessary, allowing the system to scale to multiple nodes while each individual device maintains low average energy consumption.
Data Source
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AI summary
The present application relates to signal processing technology and environmental monitoring technology and, in particular, to a system-on-chip (10), an environmental monitoring device (50; 602-1, 602-2, 602-3, 603-1, 603-2, 603-3) comprising the system-on-chip (10), and a control system (60) comprising the environmental monitoring device (50; 602-1, 602-2, 602-3, 603-1, 603-2, 603-3). A system-on-chip (10) in accordance with an aspect of the present application comprising: a communication interface (101) connected with an external bus (BUS_1); a hardware decoder (102; 20) connected with the communication interface (101); and a microprocessor core (110) connected with the communication interface (101) and the hardware decoder (102; 20), wherein the hardware decoder (102; 20) is configured to receive, via the communication interface (101), a signal frame (RX) transmitted on the external bus (BUS_1), to extract a receiver address (ADDR) from the signal frame (RX) as received and to send a wake-up command (INT) to the microprocessor core (110) upon determining that a receiver of the signal frame is the system-on-chip (10), wherein the microprocessor core (110) is configured to remain in a sleep mode until the wake-up command (INT) is received, and to perform an operation specified by a control command contained in the signal frame (RX) in response to the wake-up command.