Bus Driving Circuit Reducing Simultaneous Switching Noise
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Solution Overview
Problem
Conventional bus driving circuits face challenges in reducing simultaneous switching noise output (SSO) and power consumption, especially in high-speed data transfer applications like dynamic random access RAM (DRAM) and graphic DRAM, due to their reliance on analog majority voters which hinder high-speed operation.
Innovation Solution
A bus driving circuit incorporating a majority voter unit, latch unit, flip-flop unit, and selection unit that compares logic high and low bits, synchronizes data with a clock, and selects between original and inverted data to minimize SSO and power consumption, utilizing NMOS and PMOS transistors for efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog majority voter is used in a conventional bus driving circuit, then the circuit can determine majority logic states, but the circuit cannot operate at high speeds
Solution Approach 1:
The patent replaces the analog majority voter circuit with a digital logic-based majority voter that uses XOR gates and clock synchronization. This substitution transforms the continuous analog comparison process into discrete digital logic operations, enabling high-speed operation while maintaining the majority voting function. The digital implementation allows the circuit to operate synchronously with the clock signal, achieving high data transfer speeds.
2Object-generated harmful factors
If conventional bus driving circuits are used, then the circuit structure is simple, but simultaneous switching noise output and power consumption increase
Solution Approach 1:
The patent implements clocked synchronization where the majority voter output is latched on the rising edge of the clock signal. This periodic action ensures that multiple bits are switched simultaneously only at designated clock edges, rather than continuously during data processing. By confining switching activity to periodic clock transitions, the circuit reduces simultaneous switching noise while maintaining the ability to process high-speed data.
Solution Approach 2:
The patent introduces a latch circuit as an intermediary between the majority voter and the output buffer. This latch holds the majority vote result until the next clock edge, decoupling the continuous voting process from the output switching. The intermediary latch absorbs the timing variations and ensures clean, synchronized output transitions, thereby reducing noise while adding minimal complexity.
3Use of energy by stationary object
If conventional bus driving circuits are used, then the circuit structure is simple, but power consumption increases
Solution Approach 1:
The clocked latch circuit ensures that power-consuming switching operations occur only at discrete clock edges rather than continuously. During idle periods between clock cycles, the latch holds its state without requiring active switching, significantly reducing dynamic power consumption. This periodic operation mode maintains the necessary circuit functionality while minimizing energy dissipation from continuous switching activity.
Data Source
AI summary
A bus driving circuit includes a majority voter unit for comparing the number of logic high level bits with the number of logic low level bits among a predetermined number of bits of data; a latch unit for latching a first output signal in response to the compared result; and a flip-flop unit for latching the predetermined number of bits of data in synchronization with the clock; and a selection unit for selecting one of the latched data of the flip-flop unit and an inverted output of the latched data of the flip-flop unit according to the first output signal.