Bus Encoder Reduces I/O Power via Code Switching Frequency
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Solution Overview
Problem
Current power management systems, such as Intel DBS, primarily focus on reducing core power and do not effectively lower I/O power in computer systems, which constitutes a significant portion of total power consumption, necessitating a method to decrease I/O power while maintaining efficiency.
Innovation Solution
A method and apparatus that buffer data to be sent to a bus, encode it from n bits to n+m bits based on a specific encoding rule to lower code switching frequency, thereby reducing I/O power, utilizing an original data buffer, encoder, and encoded data buffer within the computer system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is transmitted directly without encoding, then transmission speed is fast, but I/O power consumption is high due to frequent code switching
Solution Approach 1:
The patent applies parameter changes by transforming data from n-bit format to (n+m)-bit encoded format, changing the representation parameters of data to reduce switching frequency. The encoder converts original data into encoded data with higher bit width, which reduces the frequency of code switching during transmission, thereby lowering I/O power consumption while maintaining data integrity
Solution Approach 2:
The patent introduces an encoder as an intermediary component between the data source and the bus. This encoder acts as a mediator that transforms data before transmission, reducing the switching frequency on the bus. The encoder and its associated buffers serve as intermediate elements that facilitate low-power data transmission without requiring changes to the fundamental system architecture
2Use of energy by moving object
If dynamic encoding scheme is used to lower I/O power, then power consumption decreases, but system complexity and implementation cost increase significantly
Solution Approach 1:
The patent employs dynamic buffering strategies where the encoder buffer and encoded data buffer manage data flow dynamically. The system adapts the encoding process by buffering multiple ways of data and selecting appropriate encoded representations, creating a dynamic balance between power savings and implementation complexity. This dynamic approach allows the system to achieve power reduction without requiring overly complex real-time monitoring and adjustment mechanisms
3Speed
If encoding from n bits to n+m bits is applied, then code switching frequency is reduced, but data transmission width increases
Solution Approach 1:
The patent segments the data transmission process into distinct stages: original data buffering, encoding transformation, and encoded data buffering. By dividing the data width into original n-bit segments and encoded (n+m)-bit segments, the system manages the increased width through structured segmentation. This segmentation allows the broader data width to be handled systematically through dedicated buffer structures and encoding pathways
Data Source
AI summary
The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.