Bus Encoding Using Metadata for SoC Power Reduction
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Solution Overview
Problem
The challenge in system-on-chip (SoC) applications is to reduce power consumption during data transmission across buses, as current methods do not effectively minimize power usage while maintaining efficient data communication.
Innovation Solution
The proposed solution involves compressing data using a bandwidth compression component, encoding the compressed data to reduce state transitions, and generating metadata that includes control data for decoding, which is then stored in dynamic random access memory (DRAM), thereby reducing power consumption by minimizing bus transactions and state changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is transmitted uncompressed across buses, then data communication efficiency is maintained, but power consumption increases
Solution Approach 1:
The data transmission process is segmented into compression, encoding, and metadata generation stages. The compression component divides data into smaller units that can be encoded separately, allowing selective optimization of power consumption versus communication efficiency for different data segments
Solution Approach 2:
The system changes the parameter of data representation by compressing data and encoding it with metadata before transmission. This parameter transformation reduces the volume of data transmitted across the bus, directly lowering power consumption while maintaining the ability to reconstruct and communicate the original data effectively
2Use of energy by moving object
If data is compressed and encoded before transmission, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The compression component and encoding component are merged into an integrated data processing pipeline within the electronic unit. This combination allows the system to perform both compression and encoding operations without requiring separate physical devices, thereby reducing overall system complexity while maintaining the power consumption benefits
Solution Approach 2:
The electronic unit is designed with multi-functional components that can perform compression, encoding, and metadata generation in a unified architecture. This universal design allows a single device to handle multiple data processing tasks, reducing the need for additional specialized components and thereby limiting the increase in device complexity
3Use of energy by moving object
If the number of bits transferred over buses is reduced, then power consumption decreases, but data transmission time may increase
Solution Approach 1:
Data compression and encoding are performed as preliminary actions before data transmission. By pre-processing the data to reduce its size and optimize its format, the system minimizes the amount of data that needs to be transmitted over the bus, thereby reducing power consumption during the actual transmission phase while the preliminary processing occurs in advance
Solution Approach 2:
Metadata acts as an intermediary between the compressed data and the transmission process. The metadata contains encoding information that enables efficient reconstruction of the original data at the receiving end, allowing the system to transmit fewer bits while maintaining data integrity and minimizing the time required for data reconstruction
Data Source
AI summary
Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit (EU) of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes compressing data at the EU. The method further includes encoding the compressed data at the EU. The method further includes generating control data for decoding the encoded data at the EU. The method further includes generating metadata corresponding to the compressed data at the EU. The metadata further includes the control data. The method further includes directing storage of the encoded data and the metadata in the DRAM.