Bus Encoding with Padding-Bit Inversion for Lower Memory Power
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Solution Overview
Problem
External memory accesses in computing systems consume a significant amount of power, particularly due to the capacitance of the bus, and existing bus-invert coding methods require additional hardware and become inefficient as the number of compared bits increases.
Innovation Solution
A method of encoding data values by determining if more than half of the bits in a portion of the word are ones and inverting them, with a padding bit to indicate inversion, and decoding using a corresponding padding bit to flip or maintain bits as needed, without requiring additional bus lines or specialized memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If bus-invert coding is used to reduce power consumption, then power consumption is reduced, but device complexity increases due to additional bus lines and specialized hardware
Solution Approach 1:
The patent extracts only the necessary inversion functionality from traditional bus-invert coding by using existing padding bits within data words to indicate inversion, eliminating the need for separate inversion indicator lines and reducing device complexity while maintaining power consumption benefits
Solution Approach 2:
The patent makes existing padding bits serve a dual function: their original purpose and as inversion indicators, thereby eliminating the need for additional dedicated inversion indicator lines and reducing overall device complexity
2Use of energy by moving object
If traditional bus-invert coding is used, then power consumption is reduced, but manufacturing becomes more difficult due to additional hardware requirements
Solution Approach 1:
The patent removes the requirement for specialized inversion indicator lines and dedicated inversion hardware, extracting only the essential inversion functionality that can be implemented using standard logic circuits and existing data word structures, thereby simplifying manufacturing
Solution Approach 2:
The data words themselves carry the inversion indication information through their padding bits, eliminating the need for separate specialized hardware components and making the system easier to manufacture using standard integrated circuit processes
3Measurement precision
If more bits are compared in bus-invert coding, then inversion accuracy is improved, but processing time increases
Solution Approach 1:
The patent performs inversion determination in parallel by examining padding bits that are already present in the data words, eliminating the need for sequential comparison of multiple bits and reducing processing time while maintaining accurate inversion detection
Solution Approach 2:
The patent uses only the necessary padding bits for inversion indication rather than comparing all data bits, achieving sufficient inversion accuracy with minimal processing overhead and reduced time loss
Data Source
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Figure 3
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AI summary
A method of encoding data values is described where the data values are arranged into words, each word comprising a plurality of input values and one or more padding bits. A word is encoded by determining whether more than half of bits in a portion of the word are ones, where the portion may comprise some or all of the bits of the input values in the word, and in response to determining that more than half of bits in the portion are ones, inverting all the bits in the portion and setting a corresponding padding bit to a value to indicate the inversion.