Bus Encryption Key Entropy via Address Accumulation
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Solution Overview
Problem
Existing methods for securing data communication over a bus in computing systems lack sufficient randomness in key generation, making them vulnerable to attacks, as they often rely on single addresses or pseudorandom processes, which can be predicted by attackers.
Innovation Solution
The system generates encryption keys based on multiple addresses from the address bus, introduces randomness by stalling the processor pipeline, and uses a Linear Feedback Shift Register (LFSR) to accumulate and shift address information, ensuring high entropy keys are derived locally at each module, with synchronization among bus encryption units for secure communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If pseudorandom number generators are used for key generation, then key generation is automated, but the keys can be predicted by attackers due to insufficient randomness
Solution Approach 1:
The patent introduces an LFSR as an intermediary component between the address bus and the encryption key generation. The LFSR accumulates address information over multiple bus cycles and transforms it into a high-entropy key through its internal state transitions, thereby maintaining automation while improving unpredictability
Solution Approach 2:
The system performs preliminary accumulation of address information in the LFSR before actual key generation. By collecting and processing multiple addresses in advance through the LFSR's shift and feedback operations, the system prepares high-entropy material that ensures unpredictable keys while maintaining automated operation
2Device complexity
If single addresses are used for key generation, then the key generation process is simple, but the entropy of generated keys is insufficient
Solution Approach 1:
The patent segments the key generation process into distinct phases: address collection phase, LFSR accumulation phase, and key generation phase. This segmentation allows the system to process multiple addresses through the LFSR's structured operations, increasing entropy without creating overall system complexity
Solution Approach 2:
The LFSR operates periodically, shifting and accumulating address information over multiple bus cycles. This periodic action allows the system to gather entropy from multiple addresses in a systematic manner, improving key entropy while maintaining a regular, manageable process complexity
3Reliability
If encryption keys are updated frequently, then security is improved, but synchronization complexity among bus modules increases
Solution Approach 1:
The patent implements feedback mechanisms where each module's LFSR is initialized with the same seed and processes the same address sequence. The feedback from address bus observations ensures all modules independently generate identical keys, achieving frequent updates with synchronized complexity managed through deterministic processing
Solution Approach 2:
The LFSR structure serves multiple functions: it acts as an entropy accumulator, a pseudo-random generator, and a synchronization mechanism simultaneously. This multi-functionality allows frequent key updates while reducing synchronization complexity, as the same universal structure performs all required operations across modules
Data Source
AI summary
An apparatus includes a processor and a bus encryption unit. The processor is configured to communicate information over a secured data bus, and to communicate respective addresses over an address bus. The bus encryption unit is configured to generate an encryption key based on multiple addresses that appeared on the address bus, and to encrypt the information communicated between the processor and the secured data bus with the encryption key.