Bus Frequency Scaling via Pending Load Prediction

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Solution Overview

Problem

Existing frequency control methods for bus clock frequencies in computing devices are either power-intensive or performance-degrading, as they rely on past load predictions that are often less than optimal.

Innovation Solution

A method that calculates an expected load value based on pending bytes and active time to adjust bus frequencies dynamically, decreasing frequency if load is low, increasing if high, and maintaining if within thresholds, using a block-aware governor to send frequency adjustment signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If the bus clock frequency is lowered to reduce power consumption, then power consumption is reduced, but latency increases beyond requirements and performance degrades

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

The bus clock frequency is made dynamic rather than static, allowing it to change based on predicted future load conditions. The system transitions between different frequency states (low, medium, high) depending on the expected workload, optimizing the balance between power consumption and performance for each specific condition.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary actions by predicting future bus load before the actual workload arrives. By analyzing pending load values and historical traffic patterns, the system anticipates upcoming traffic conditions and adjusts the clock frequency in advance, ensuring optimal performance when the actual load occurs while avoiding unnecessary high-frequency operation during low-load periods.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the bus clock frequency is set to higher frequencies to reduce latency and provide performance margin, then performance is improved, but power consumption increases

Engineering Contradiction:
ImproveperformanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The system changes the operating parameter (clock frequency) based on predicted future load conditions rather than maintaining a fixed high frequency. By adjusting the frequency parameter dynamically according to actual needs, the system achieves high performance when required while consuming less power during low-load periods, directly resolving the trade-off between performance and power consumption.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If frequency selection is based on past load to predict future load, then frequency adjustment is simplified, but the prediction accuracy becomes less than optimal

Engineering Contradiction:
Improvefrequency control complexityVSAvoidload prediction accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The system implements feedback by continuously monitoring actual bus traffic and comparing it with predicted load values. This feedback mechanism allows the system to refine its predictions over time and adjust frequency selections based on both historical patterns and real-time conditions, improving prediction accuracy while maintaining manageable control complexity through systematic analysis of multiple parameters.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system adds another dimension to frequency control by considering multiple factors simultaneously (pending load values, historical traffic patterns, current system state) rather than relying solely on simple past load averaging. This multi-dimensional approach enables more accurate predictions while keeping the control logic structured and manageable through systematic evaluation of diverse parameters.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10102173B2Pending load based frequency scaling
Publication Date: 2018.10.16 QUALCOMM INNOVATION CENTER INC
  • US10102173B2 patent drawing
  • US10102173B2 patent drawing
  • US10102173B2 patent drawing

AI summary

Methods and devices for controlling frequency of a bus are disclosed. A method may include determining a total-pending load value indicative of a number of a bytes that will pass through the bus in the future and calculating an expected load value based upon i) the total-pending load value, ii) a number of bytes that passed through the bus during a prior time window, and iii) a time duration the bus was active during the prior time window. The frequency of the bus is decreased if the expected load value is less than a lower threshold and increased if the expected load value is greater than an upper threshold. A frequency of the bus is maintained if the expected load value is greater than the lower threshold and less than the upper threshold.