Bus Functional Model for PLD Simulation Verification
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Solution Overview
Problem
The verification of design blocks in processor-based systems is time-consuming and expensive due to slow simulation speeds and the need for indirect control of interface bus transactions, especially when simulating complex processor interactions and coordinating control between interface buses and input/output interfaces.
Innovation Solution
A simulation environment is created using functional models that emulate processor interactions, input/output interfaces, and memory subsystems, controlled by scripts that specify transactions and utilize a synchronization bus for efficient synchronization, allowing for direct control and validation of transactions across multiple interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a processor is simulated to verify a design block, then the verification can be performed with realistic processor behavior, but the simulation speed becomes slow due to the complexity of simulating the processor
Solution Approach 1:
The patent creates a simplified copy of the processor called a 'bus functional model' that replicates only the essential bus interface behaviors needed for design block verification. This model copies the processor's bus transaction capabilities, protocol handling, and exception generation without implementing the full processor architecture, thereby achieving verification accuracy for bus-related defects while dramatically improving simulation speed.
Solution Approach 2:
The patent extracts only the necessary bus interface functionality from the complete processor model. The bus functional model isolates and implements specifically the bus master and bus target behaviors, transaction issuance, protocol compliance, and exception handling capabilities that are relevant to design block verification, removing all other processor functions that would slow down simulation.
2Reliability
If indirect control of transactions is used through the processor, then the design block can be verified in a realistic processor environment, but the verification process becomes time-consuming and expensive
Solution Approach 1:
The bus functional model serves as an intermediary between the test environment and the design block. It directly controls bus transactions, exception conditions, and protocol scenarios without requiring processor intervention. This intermediary model enables direct specification of test cases including normal operations, exceptional conditions like aborts and retries, and error conditions such as bus parity errors, significantly reducing verification time while maintaining completeness.
3Reliability
If coordination of control and validation between interface bus and input/output interface is performed, then defects in the design block can be detected, but the coordination process becomes time-consuming and expensive
Solution Approach 1:
The patent merges the control and validation of both the interface bus and input/output interface into a single integrated bus functional model. This unified model simultaneously manages transactions on both interfaces, coordinates their interactions, and validates design block behavior across the entire interface chain. The synchronization bus coordinates timing between interfaces, eliminating the need for separate complex coordination mechanisms and reducing overall system complexity while maintaining comprehensive defect detection capability.
Data Source
AI summary
A method is provided for building a simulation environment. A first functional model is produced that emulates the interaction of a processor with a first interface of a bus for the processor as controlled by a first script. A second functional model is produced that is controllable to emulate multiple interfaces. The second functional model is controlled to emulate a second interface of an input/output peripheral by a second script. A third functional model is produced that emulates a memory subsystem. A simulation environment is automatically generated that simulates the design block for a programmable logic device. The simulation environment couples the bus to the design block and the first and third functional models, couples the second interface to the design block and the second functional model, and couples the first and second functional models via a synchronization bus used for synchronizing between transactions of the first and second scripts.