Bus Interconnect Enforcing Strongly-Ordered Memory Requests
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Solution Overview
Problem
Weakly-ordered processing systems lack efficient methods to enforce ordered memory operations, leading to unpredictable program behavior and performance inefficiencies, particularly in systems with multiple memory devices where memory barriers need to be issued to every accessible memory device.
Innovation Solution
A bus interconnect system that includes a controller to enforce ordering constraints on memory access requests by using attributes to indicate strongly-ordered requests, ensuring that such requests are executed before other operations, and generating memory barriers only for non-target memory devices accessible by the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory barriers are issued to every accessible memory device to enforce ordering constraints, then strongly-ordered memory operations are ensured, but system performance deteriorates due to the overhead of issuing barriers to multiple devices
Solution Approach 1:
The patent applies local quality by making the memory barrier enforcement selective rather than universal. The bus interconnect controller detects the strongly-ordered attribute on specific memory access requests and issues memory barriers only to the target memory device of that specific request, rather than to all accessible memory devices. This localized approach maintains the required ordering guarantee while reducing the performance overhead associated with broadcasting barriers system-wide.
2Reliability
If memory operations are delayed to maintain ordering, then program behavior predictability is improved, but execution speed decreases
Solution Approach 1:
The patent applies dynamics by enabling the processing system to adaptively enforce ordering constraints based on the specific attributes of memory access requests. The bus interconnect controller dynamically determines whether to enforce ordering on a per-request basis by checking for the strongly-ordered attribute, rather than applying a static ordering policy to all memory operations. This dynamic approach allows the system to maintain predictability where required while preserving execution speed for operations that do not require strict ordering.
Data Source
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AI summary
The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.