SoC Bus Interconnector Synchronization Block for Burst Data
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Solution Overview
Problem
In system-on-chip (SoC) design, existing bus systems face challenges in efficiently managing data transfer between master and slave devices, particularly in preventing transfer delays and deadlocks, especially when handling burst data operations.
Innovation Solution
A bus system with an interconnector that includes a synchronization/compaction block to control the transfer of write requests and data, buffering write requests and data, and adjusting transfer paths based on priority and availability, ensuring synchronized transfer without delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the master device performs burst transfer operations, then data transfer throughput is improved, but transfer delays and deadlocks may occur
Solution Approach 1:
The synchronization/compaction block performs preliminary actions by buffering write requests and write data separately before transfer, predicting when data will be available, and preparing the transfer path in advance. This prevents delays by ensuring both request and data are ready before initiating transfer to the slave device.
Solution Approach 2:
The synchronization/compaction block acts as an intermediary between the master device and slave device, managing the buffering and coordination of write requests and write data. It mediates the transfer process by controlling when data is held in buffers and when transfers are initiated, preventing deadlocks through proper sequencing.
2Loss of time
If write requests are transferred immediately without waiting for write data, then response time is improved, but data integrity is compromised
Solution Approach 1:
The system performs preliminary buffering of write requests and write data separately, allowing the write request to be prepared and buffered in advance while the actual data is being generated or becomes available. This preliminary action enables faster response time without compromising data integrity.
Solution Approach 2:
The transfer process is segmented into separate buffering stages for write requests and write data. The write request can be buffered and prepared independently, then transferred to the slave device at the appropriate time when the data is ready, maintaining both responsiveness and data integrity.
3Reliability
If buffers are sized to accommodate all burst data, then transfer synchronization is improved, but device complexity increases
Solution Approach 1:
The buffer sizes are configured dynamically based on the predicted length of burst data rather than being fixed for all cases. The synchronization/compaction block adapts the buffer capacity to match the actual data transfer requirements, achieving reliable synchronization without unnecessarily large buffers that would increase complexity.
Solution Approach 2:
The system changes the parameter of buffer size based on the characteristics of the burst data being transferred. By adjusting buffer capacity to match the predicted burst length, the system achieves effective synchronization while avoiding the complexity of oversized buffers designed for worst-case scenarios.
Data Source
AI summary
A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the slave device.