Programmable Bus Interconnects With Bypass Routing for Timing Closure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programmable integrated circuits face inefficiencies in routing long wide connections, leading to routing congestion and timing closure problems, particularly when handling bus interconnections, which increases development time.
Innovation Solution
The integration of logic regions with global interconnects, input selection circuitry, and output selection and routing circuitry, including bypass paths, allows for efficient routing of signals and configuration of bus interconnections, enabling direct access to registers and output drivers to bypass processing steps when necessary, thereby reducing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If point-to-point connections are used for routing signals in conventional programmable circuits, then routing flexibility is provided, but routing congestion and timing closure problems occur when handling long wide connections such as bus interconnections
Solution Approach 1:
The patent merges multiple point-to-point connection resources into a unified bus interconnection structure. Logic regions are equipped with bus interface circuitry that can simultaneously establish multiple point-to-point connections through shared bus resources, enabling efficient wide bus interconnections while maintaining routing flexibility. This resolves the contradiction by combining the flexibility of point-to-point routing with the efficiency of bus-based wide connections.
2Ease of operation
If conventional point-to-point interconnects are used, then individual signal routing is achieved, but development time increases due to routing congestion and timing closure problems
Solution Approach 1:
The patent implements universal bus interconnection resources that can serve multiple logic regions simultaneously. The bus interface circuitry in each logic region can configure connections to shared bus resources, allowing a single bus infrastructure to handle multiple signal routing requirements. This multi-functional approach reduces development time by eliminating the need to create separate routing paths for each signal while maintaining full routing capability.
3Adaptability or versatility
If direct bus interconnections are implemented without bypass paths, then signal routing through logic regions is achieved, but signal delay increases due to unnecessary processing steps
Solution Approach 1:
The patent segments the signal path into two distinct modes: a full processing path through logic regions and a direct bypass path. The bus interface circuitry includes bypass logic that can selectively route signals directly between logic regions without passing through intermediate processing stages. This segmentation allows the system to choose the fastest path depending on whether processing is needed, thereby maintaining both routing flexibility and high signal transmission speed.
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
Integrated circuits may include logic regions configurable to perform custom functions. Interconnects (16, 16C, 16D, 16E) may be used to route signals throughout the integrated circuit. The logic region (34) may be coupled to input selection circuitry (55) for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry (56) for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry (38) may provide direct access to registers inside the logic regions (34) and to the output selection and routing circuitry (56) by bypassing the input selection circuitry and other processing circuitry inside the logic regions (34). Bus interconnections having logic regions performing register pipelining, wire stitching, and acting as data source/sink stations to get on and off the bus interconnections may be generated by configuring the bypass circuitry and the output selection and routing circuitry appropriately.