Bus Interface Logic Burst Order Configuration
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Solution Overview
Problem
Current microprocessor systems incur stall cycles due to non-optimum ordering of cache line reads, with existing protocols limiting dynamic specification of data entity transfer ordering, leading to suboptimal performance in various scenarios.
Innovation Solution
A microprocessor with bus interface logic that allows dynamic specification of burst orders during the request phase, enabling interleaved, linear, nibble linear, or custom ordering of data transfers, while maintaining compatibility with existing bus protocols, through configuration of machine-specific registers and request packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If linear ordering is used for data transfer, then data proximity is maximized and processing stalls are minimized in most cases, but when the critical quadword is the last quadword rather than the first, numerous pipeline stalls are incurred
Solution Approach 1:
The system dynamically selects between linear ordering and interleaved ordering based on the position of the critical quadword. The bus interface logic determines the optimal ordering scheme at runtime, switching between fixed ordering patterns to minimize pipeline stalls regardless of which quadword is critical.
Solution Approach 2:
The invention changes the ordering parameter (linear vs. interleaved) based on the critical quadword position. By monitoring which quadword is critical and adjusting the transfer ordering accordingly, the system optimizes performance for both cases where the first or last quadword is critical.
2Reliability
If interleaved ordering is used for data transfer, then wait states are precluded in older DRAM designs, but linear ordering is optimal from the standpoint of data proximity in the majority of cases
Solution Approach 1:
The system dynamically selects between linear ordering and interleaved ordering based on the position of the critical quadword. The bus interface logic determines the optimal ordering scheme at runtime, switching between fixed ordering patterns to minimize pipeline stalls regardless of which quadword is critical.
Solution Approach 2:
The invention changes the ordering parameter (linear vs. interleaved) based on the critical quadword position. By monitoring which quadword is critical and adjusting the transfer ordering accordingly, the system optimizes performance for both cases where the first or last quadword is critical.
3Device complexity
If a fixed ordering protocol is implemented, then system simplicity is maintained, but dynamic optimization of data transfer ordering is not possible
Solution Approach 1:
The system dynamically selects between linear ordering and interleaved ordering based on the position of the critical quadword. The bus interface logic determines the optimal ordering scheme at runtime, switching between fixed ordering patterns to minimize pipeline stalls regardless of which quadword is critical.
Data Source
AI summary
A microprocessor including a cache memory and bus interface logic. The bus interface logic is interfaced with request signals and data signals and includes a request interface and a response interface. The request interface provides a request via the request signals for a data transaction in which the request specifies a selected burst order. The response interface stores data received via the data signals into the cache memory according to the selected burst order. The request interface may specify the selected burst order by configuring a field of a request packet during a request phase of the data transaction. The selected burst order may selected from any of several different data transaction orderings, including an interleaved order, a linear order, a nibble linear order and a custom order. The microprocessor may further include instruction logic which provides an instruction to the bus interface logic specifying the selected burst order.