Bus Interface Circuit Galvanic Isolation Area Reduction
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Solution Overview
Problem
Existing bus interface circuits require multiple galvanically isolating components for each data stream, leading to high chip area requirements and inefficiencies in transmitting multiple data streams across different voltage domains.
Innovation Solution
A bus interface circuit design that uses a single galvanically isolating component for multiple data streams by coding and decoding data streams to assign symbols to edges or levels, ensuring deterministic delays to avoid collisions and maintain low jitter, allowing simultaneous transmission of high-priority and low-priority data streams via the same isolating component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple galvanically isolating components are used for each data stream, then reliable galvanic isolation and overvoltage protection are achieved, but chip area requirement increases significantly
Solution Approach 1:
The patent merges multiple data streams (first data stream and at least one further data stream) into a single symbol sequence that is transmitted through one galvanically isolating component. This combining approach maintains the galvanic isolation function while eliminating the need for multiple separate isolating components, thereby reducing chip area.
Solution Approach 2:
The single galvanically isolating component is designed to handle multiple data streams simultaneously by encoding them into a unified symbol sequence. This multi-functional approach allows one component to perform the isolation function for what would traditionally require multiple components, reducing overall device complexity and area.
2Area of stationary object
If multiple data streams are transmitted via the same galvanically isolating component, then chip area is reduced, but signal collisions and jitter may increase
Solution Approach 1:
The coding circuit performs preliminary encoding of multiple data streams into a symbol sequence before transmission through the galvanically isolating component. This pre-processing ensures that signals from different data streams are properly formatted and timed, preventing collisions and maintaining signal integrity during transmission.
Solution Approach 2:
The system dynamically manages the transmission of multiple data streams by assigning different symbols to different data streams and controlling their timing. The coding circuit adapts the symbol sequence construction to ensure that high-priority data streams maintain deterministic delays while low-priority streams are transmitted without causing collisions, thus maintaining signal integrity.
3Reliability
If high-priority data streams are transmitted with deterministic delays, then low jitter is achieved, but transmission latency increases
Solution Approach 1:
The patent applies different quality requirements to different data streams: high-priority data streams receive deterministic delay treatment to ensure low jitter, while low-priority data streams are transmitted with more flexible timing. This localized quality approach ensures that jitter-critical streams maintain performance without unnecessarily increasing latency for all streams.
Solution Approach 2:
The system changes the timing parameter dynamically based on data stream priority. For high-priority streams, a fixed deterministic delay is applied to eliminate jitter. For low-priority streams, the delay is adjusted or minimized. This parameter variation allows the system to achieve low jitter for critical streams without imposing uniform latency penalties on all transmissions.
Data Source
AI summary
A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.