Bus Interface Circuit Destination-Based Clock Gating

Solution Overview

Problem

Existing bus interface circuits in control systems with multiple slave devices face challenges in reducing current consumption and noise, particularly when data is intended for a specific slave device, as they continue to consume power and generate noise even when the data is not destined for them.

Innovation Solution

The bus interface circuit includes a head information detection circuit, an inner clock control circuit, and a data analyzing circuit that synchronizes with the clock signal only when data is intended for the specific slave device, stopping the inner clock signal when the destination mismatch occurs, thereby reducing power consumption and noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the bus interface circuit continuously monitors and processes data from the data channel, then data processing capability is maintained, but current consumption and noise increase when data is not intended for the specific slave device

Engineering Contradiction:

Improvedata processing capabilityVSAvoidcurrent consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The circuit performs preliminary action by detecting destination information before fully processing the data. The destination detection circuit examines the destination information in the head information to determine whether the data is intended for this slave device before the data analyzing circuit processes the data body, thereby avoiding unnecessary power consumption when data is not destined for this device

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The inner clock signal generation is made dynamic rather than static. The inner clock control circuit enables or disables the inner clock signal based on whether the destination information matches the current slave device. When data is not intended for this device, the inner clock signal is stopped, dynamically reducing power consumption while maintaining data processing capability when needed

Inventive Principle:

Principle #15Dynamics

2Productivity

If the bus interface circuit continuously processes data, then data processing capability is maintained, but noise increases when data is not intended for the specific slave device

Engineering Contradiction:

Improvedata processing capabilityVSAvoidnoise

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The circuit performs preliminary action by detecting destination information before fully processing the data. The destination detection circuit examines the destination information in the head information to determine whether the data is intended for this slave device before the data analyzing circuit processes the data body, thereby avoiding unnecessary noise generation when data is not destined for this device

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The inner clock signal generation is made dynamic rather than static. The inner clock control circuit enables or disables the inner clock signal based on whether the destination information matches the current slave device. When data is not intended for this device, the inner clock signal is stopped, dynamically reducing noise while maintaining data processing capability when needed

Inventive Principle:

Principle #15Dynamics

3Productivity

If the data analyzing circuit operates continuously, then data processing capability is maintained, but power consumption increases when destination does not match

Engineering Contradiction:

Improvedata processing capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The circuit performs preliminary action by detecting destination information before fully processing the data. The destination detection circuit examines the destination information in the head information to determine whether the data is intended for this slave device before the data analyzing circuit processes the data body, thereby avoiding unnecessary power consumption when data is not destined for this device

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The inner clock signal generation is made dynamic rather than static. The inner clock control circuit enables or disables the inner clock signal based on whether the destination information matches the current slave device. When data is not intended for this device, the inner clock signal is stopped, dynamically reducing power consumption while maintaining data processing capability when needed

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9971717B2Bus interface circuit

Publication Date: 2018.05.15 KK TOSHIBA

AI summary

According to an embodiment, a bus interface circuit disposed in each of a plurality of slave devices to which a common data channel and a clock channel are supplied from a master device includes a head information detection circuit, an inner clock control circuit, and a data analyzing circuit. The head information detection circuit detects head information from the data channel indicating a head of the data from the data channel, destination information indicating a destination of the data, and a data body in this order. The data analyzing circuit is synchronized with the inner clock generated from the clock control circuit after the head information is detected, and detects the destination information from the data channel, and then analyzes the data body. The inner clock control circuit stops the inner clock when the destination information does not match the destination information of the bus interface circuit.