Bus Interface Compression for Hybrid Video Processing Bottlenecks

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Solution Overview

Problem

Hybrid data processing architectures face challenges with high bandwidth consumption and bottlenecks in bus interfaces due to the communication of decoded video and inference results between integrated and discrete processors, limiting the number of video streams that can be processed concurrently.

Innovation Solution

Implementing interface data compression techniques at the system bus interface, such as PCIe, through initial compression negotiation and dynamic adaptation based on compression context changes, using resident algorithms or downloadable software to optimize data transfer between host and secondary devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hybrid data processing architecture is used to implement media analytics applications, then compute capability and processing flexibility are improved, but bandwidth consumption and bus interface bottlenecks increase

Engineering Contradiction:
Improvecompute capabilityVSAvoidbandwidth consumption
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent extracts the compression function from the main data processing flow and implements it as a separate interface compression subsystem. This subsystem is specifically dedicated to compressing data at the bus interface between integrated and discrete processors, removing the bandwidth bottleneck without affecting the hybrid processing architecture's compute capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The interface compression subsystem acts as an intermediary between the integrated processor and discrete processor. It compresses data before transmission across the bus interface and decompresses received data, mediating the data exchange to reduce bandwidth consumption while maintaining processing flexibility

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If more video streams are processed concurrently in hybrid architecture, then processing throughput is improved, but bus interface bandwidth requirements and power consumption increase

Engineering Contradiction:
Improveprocessing throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The compression subsystem dynamically adapts its operation based on the data being processed. It negotiates compression algorithms with the remote processor and adjusts compression levels according to the specific video stream characteristics and processing requirements, enabling efficient handling of multiple concurrent streams with optimized power consumption

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If interface data compression is implemented, then bandwidth consumption is reduced, but device complexity and implementation overhead increase

Engineering Contradiction:
Improvebandwidth consumptionVSAvoidimplementation overhead
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The interface compression subsystem is designed to be universal and compatible with existing hybrid data processing architectures. It can negotiate and use multiple different compression algorithms, making it adaptable to various processor types and data formats without requiring fundamental changes to the underlying architecture

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The compression subsystem performs self-configuration through negotiation with the remote processor. It automatically selects appropriate compression algorithms and parameters based on the data being transmitted, eliminating the need for manual configuration and reducing implementation overhead

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250226841A1Interface data compression for hybrid data processing architectures
Publication Date: 2025.07.10 INTEL CORP
  • US20250226841A1 patent drawing
  • US20250226841A1 patent drawing
  • US20250226841A1 patent drawing

AI summary

Systems, apparatus, articles of manufacture, and methods to provide interface data compression for hybrid data processing architectures are disclosed. An example apparatus disclosed herein includes communicates with a device to determine interface compression capability information, The disclosed example apparatus also determines, based on the interface compression capability information, whether a host and the device implement one or more interface compression algorithms in common, the one or more interface compression algorithms to provide data compression over a bus interface between a host and the device. The disclosed example apparatus further configures, in response to a determination that the host and the device implement one or more interface compression algorithms in common, a first interface compression algorithm of the one or more interface compression algorithms to operate on the host and on the device to compress data communicated over the bus interface.