Bus Interface Error Correction Parallel Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error correction methods for memory devices increase data latency and reduce system efficiency due to the need for extensive combinatorial logic operations during data retrieval, leading to prolonged wait states for processors.
Innovation Solution
The method involves retrieving raw data before performing error correction and outputting it during the same operational phase, allowing error processing to occur in parallel with data transfer, utilizing a hardware module with combinational logic elements to calculate and apply error correction data during the data transfer phase, thereby reducing wait states and improving system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed each time data is read from memory, then memory reliability is improved, but data latency increases and system efficiency is reduced
Solution Approach 1:
The patent applies preliminary action by performing error correction during the data write operation before the data is stored in memory. The error correction code is calculated and stored alongside the data, so that when the data is read back, the correction has already been prepared in advance, eliminating the need for time-consuming correction operations during the read phase.
Solution Approach 2:
The patent implements continuity of useful action by overlapping the error correction calculation with the data write operation. Instead of performing error correction as a separate sequential step that increases latency, the correction code generation occurs concurrently with data storage, maintaining continuous productive action without interruption.
2Reliability
If extensive combinatorial logic operations are performed during data retrieval for error correction, then error detection and correction capability is improved, but the number of wait states increases
Solution Approach 1:
The error correction code is calculated and prepared in advance during the write phase, storing the correction information with the data. This preliminary preparation eliminates the need for extensive combinatorial logic operations during the read phase, as the correction data is already available when needed.
Solution Approach 2:
The patent creates a copy of the error correction code and stores it with the data in memory. This copied correction information can be quickly retrieved and applied without performing complex real-time calculations, significantly reducing the computational burden during data retrieval operations.
3Reliability
If error correction code data is stored with memory locations, then error detection capability is improved, but memory storage requirements increase
Solution Approach 1:
The patent employs Hamming code error correction, which uses a specific ratio of data bits to correction bits (e.g., 7 data bits require 4 correction bits). This parameter optimization provides effective error detection and correction capability while minimizing the additional storage overhead, achieving a balance between reliability and storage efficiency.
Data Source
AI summary
A method of error correction includes retrieving raw data from a memory device during a first operational phase of the error correction device. The raw data is retrieved by a bus interface device that interfaces with a variety of memory devices. During a second operational phase, the raw data is outputted from the bus interface device to the bus master. In addition, error correction data is calculated, and error correction is performed on the raw data during the second operational phase. By retrieving the raw data before performing error correction, and by outputting the raw data during the same operational phase, data may be retrieved from the memory more rapidly.