Bus Interface Unit Arrangement for Semiconductor Memory High Speed
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Solution Overview
Problem
Existing semiconductor memory devices face difficulties in arranging internal buses and interface circuits to achieve high-speed data transfer with large-capacity memory cell arrays and multiple data input/output terminals, especially when requiring higher data transfer rates or more memory cell array banks.
Innovation Solution
A semiconductor memory device design featuring a memory cell array section connected to a peripheral circuit section via an internal bus, with a bus interface unit that converts serial data to parallel data and vice versa, and external input/output buffers arranged in a line, where the bus interface unit is densely placed in a narrower area than the buffers to shorten signal wiring lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bus interface unit is arranged in a wide area to accommodate multiple external input/output buffers, then the number of data terminals increases, but the wiring length increases and data transfer speed decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of buffers to a three-dimensional stacked configuration. Multiple external input/output buffers are arranged in different layers vertically, allowing the bus interface unit to access buffers from multiple dimensions simultaneously. This dimensional change reduces the horizontal wiring length while maintaining the number of data terminals.
Solution Approach 2:
The bus interface unit is positioned to overlap with multiple external input/output buffers in the vertical dimension. The buffers are nested in different layers, with the bus interface unit accessing them through vertical wiring. This nesting arrangement allows multiple buffers to share the same horizontal footprint, reducing overall wiring length.
2Quantity of substance
If more memory cell array banks are included to increase capacity, then memory capacity increases, but the complexity of arranging internal buses and interface circuits increases
Solution Approach 1:
The memory system is divided into multiple independent memory cell array banks, each capable of parallel operation. The bus interface unit is segmented to handle multiple banks simultaneously, with each buffer layer dedicated to specific banks. This segmentation allows independent optimization of each bank's connection path, reducing overall arrangement complexity.
Solution Approach 2:
The bus interface unit is designed with multi-functional capability to interface with multiple memory cell array banks through a unified architecture. The same bus interface unit can serve different banks by switching between them, reducing the need for separate interface circuits for each bank and thereby reducing overall complexity.
3Speed
If the data transfer rate is increased to achieve high-speed operation, then data transfer speed improves, but power consumption increases
Solution Approach 1:
The patent enables continuous data transfer operations by maintaining persistent connections between memory banks and the bus interface unit through the stacked buffer architecture. Data can be transferred continuously without repeated setup overhead, improving effective transfer rate while reducing peak power consumption through steady-state operation.
Solution Approach 2:
Data transfer is segmented into parallel channels through multiple buffers and memory banks operating simultaneously. This segmentation distributes the power consumption across multiple lower-power parallel operations rather than requiring one high-power sequential operation, achieving high effective transfer rates with reduced overall power consumption.
Data Source
AI summary
A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus connecting the plurality of memory cell arrays and the peripheral circuit section. The peripheral circuit section includes external input/output buffers, and bus interface circuits. The bus interface circuits execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers. The bus interface circuits are densely arranged between the internal bus and the input/output buffers, so that a width d1 of the area of the plurality of bus interface circuits being arranged is narrower than a width d2 of the area of the external input/output buffers being arranged and a bus width maximum value d3 of the internal bus.