Bus Interface Circuit Pin Reversal Detection

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Solution Overview

Problem

Conventional MIPI RFFE bus systems face challenges in distinguishing between identical RFFE slave devices, leading to potential bus conflicts due to identical devices sharing the same SCLK and SDATA signals, which can prevent the RFFE master interface from addressing them uniquely.

Innovation Solution

The solution involves configuring RFFE slave interfaces to determine if the CLK and DATA pins are reversed, allowing them to reprogram their slave or product IDs, thereby becoming independently addressable by the RFFE master interface, without the need for additional pins or manipulating the power supply voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If identical RFFE slave devices share the same SCLK and SDATA signals, then device complexity is reduced and manufacturing is simplified, but bus conflicts occur and unique addressing becomes impossible

Engineering Contradiction:
Improvedevice complexityVSAvoidbus conflict prevention
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The slave device detects the start sequence and determines pin assignments before normal bus operations begin. This preliminary detection and routing configuration prevents bus conflicts from occurring during subsequent communications by ensuring proper signal routing is established in advance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The slave device autonomously detects whether CLK and DATA pins are reversed through start sequence analysis, automatically determines the correct pin assignment, and configures its own internal routing without external intervention. This self-service capability eliminates bus conflicts while maintaining device simplicity.

Inventive Principle:
Principle #25Self-service

2Reliability

If additional pins are added to distinguish identical slave devices, then unique addressing is enabled, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveunique addressing capabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of adding physical distinguishing features or additional pins to identical slave devices, the system uses software-based identification through start sequence detection and pin assignment determination. The identical hardware copies are differentiated through their electrical signal characteristics during the detection phase, avoiding any physical modifications.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The invention changes the electrical parameters (signal timing, voltage levels, or transition patterns) detected during the start sequence to determine pin assignments. By analyzing these parameter variations, the system can uniquely identify and address identical devices without adding physical components.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If power supply voltage is manipulated to distinguish slave devices, then unique addressing is achieved, but system complexity and potential reliability issues increase

Engineering Contradiction:
Improveunique addressing capabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention replaces the mechanical/electrical approach of manipulating power supply voltage with a signal-based detection method. Instead of changing voltage levels to distinguish devices, the system analyzes the start sequence signals already present on the bus, substituting a simpler signal analysis mechanism for a more complex power manipulation approach.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9817782B2System and method for a bus interface
Publication Date: 2017.11.14 INFINEON TECHNOLOGIES AG
  • US9817782B2 patent drawing
  • US9817782B2 patent drawing
  • US9817782B2 patent drawing

AI summary

In accordance with an embodiment, a method of operating a bus interface circuit includes detecting a start sequence on a plurality of input terminals, determining whether a first input terminal and a second input terminal is a data terminal and a clock terminal, respectively, or whether the first input terminal and the second terminal is a clock terminal and a data terminal, respectively. The method also includes routing the first input terminal to a data terminal and the second input terminal to a clock terminal if first input terminal and the second input terminal are determined to be a data terminal and a clock terminal, respectively, and routing the first input terminal to the clock terminal and the second input terminal to the data terminal if first input terminal and the second input terminal are determined to be a clock terminal and a data terminal, respectively.