Bus Inversion Encoder Using Future Data for Low-Latency Memory Buses
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Solution Overview
Problem
Existing bus inversion encoding systems for high-bandwidth memory face challenges such as increased power consumption, heat generation, and high latency due to the need for majority voters and sequential operations.
Innovation Solution
A bus inversion encoder module that utilizes future data in a data bus with a serializer, comparing current data with past and future data to encode current data with minimal latency and high transition reduction efficiency, replacing complex majority voters with simpler circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If majority voters are used to determine inversion by comparing current data with past data, then transition reduction is achieved, but device complexity and area increase significantly
Solution Approach 1:
The patent segments the data bus into multiple channels and processes inversion determination independently for each channel. Instead of using complex majority voters that compare all bits simultaneously, the system divides the inversion determination into simpler per-channel operations, reducing overall circuit complexity while maintaining transition reduction effectiveness
Solution Approach 2:
The patent inverts the traditional approach by determining inversion status for each channel independently rather than using majority voting across all channels. This reverse approach simplifies the circuit by eliminating the need for complex majority voter logic while achieving the same transition reduction goal through a different computational paradigm
2Area of stationary object
If sequential operations are used in bus inversion encoding, then area is reduced, but latency increases
Solution Approach 1:
The patent performs preliminary actions by pre-determining inversion status for each channel before the actual data transmission. By preparing the inversion decisions in advance for each channel independently, the system eliminates latency-critical sequential operations while maintaining reduced area through the use of simple per-channel logic rather than complex parallel majority voters
3Loss of energy
If future data is utilized in encoding current data, then transition reduction efficiency improves, but latency increases due to additional encoding time
Solution Approach 1:
The patent applies preliminary action by determining inversion status for future data channels in advance, before the current data needs to be transmitted. This allows the system to prepare inversion decisions that will be needed for future transmissions, improving transition reduction efficiency without adding latency to current data encoding since the preparation happens independently and in advance for each channel
Data Source
AI summary
Disclosed are a bus inversion encoder module that utilizes future data in a data bus including a serializer with minimum latency and high transition reduction efficiency by comparing current data with both past data and the future data and encoding the current data, and a bus inversion system including the same. The bus inversion encoder module uses current data, past data, and future data transmitted through a bus and each including a plurality of bits, determines whether to invert the current data, and generates a current flag and coded current data by using whether to invert, an output flag, and the current data. The output flag is generated by summing the current flag and the coded current data and serially converting the current flag and the coded current data.