Data Bus Inversion Detection Using XOR Bitwise Comparison
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Solution Overview
Problem
Current data bus inversion mechanisms in microprocessors are inefficient when using domino logic design techniques, leading to increased latency and power consumption due to the need for additional gate delays and the inability to count all bits in a signal group, particularly in high-speed bus systems.
Innovation Solution
A bus inversion apparatus and method that uses a combination of exclusive-OR gates and inversion detectors with logical shift circuits to perform bitwise comparisons and count all bits in a signal group, eliminating the need for full adders and reducing the number of XOR operations, allowing for efficient data bus inversion using domino logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full adders are employed to count the number of asserted bits in the exclusive-OR result bus, then the counting function is achieved, but additional gate delays are introduced increasing latency
Solution Approach 1:
The patent divides the 16-bit exclusive-OR result bus into four separate 4-bit subgroups. Each subgroup is counted independently using simplified logic circuits rather than a single complex full adder chain. This segmentation reduces the critical path delay while maintaining accurate counting of all bits that will change state.
Solution Approach 2:
The patent uses a threshold-based inversion decision (inverting when more than 8 bits change) rather than counting every single changed bit exactly. This partial counting approach combined with threshold comparison achieves the bus inversion function with reduced counting complexity and lower latency compared to precise full counting.
2Measurement precision
If 1-bit adders are employed in the first stage to add asserted bits, then counting is performed, but the structure becomes complex and domino logic implementation becomes difficult
Solution Approach 1:
The patent segments the counting function into four independent 4-bit counters instead of using a hierarchical structure of 1-bit adders feeding into 2-bit adders and so on. Each 4-bit counter uses simplified logic that is much more compatible with domino logic implementation, reducing overall circuit complexity while maintaining counting accuracy.
Solution Approach 2:
The patent changes the counting parameter from counting individual bits sequentially through multiple adder stages to counting 4-bit subgroups in parallel using simplified logic. This parameter change in the counting approach reduces circuit complexity and enables easier domino logic implementation.
3Loss of energy
If the current bus inversion mechanisms are used, then power consumption and noise are minimized, but latency increases and domino logic implementation becomes inefficient
Solution Approach 1:
By segmenting the bus inversion detection into four independent 4-bit subgroup detectors, the patent enables parallel processing of changed bits. This segmentation reduces the overall detection latency while maintaining the power-saving benefits of bus inversion, as the parallel structure completes counting faster without requiring excessive gate delays.
Solution Approach 2:
The patent uses a threshold-based inversion decision (more than 8 bits changed) rather than precise counting of every changed bit. This partial counting approach reduces the counting complexity and latency while still achieving effective bus inversion for power consumption and noise minimization in high-speed systems.
Data Source
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AI summary
A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comparison of the data buses, and provide an exclusive-OR bus. The states of the exclusive-OR bus indicate whether corresponding bits of the data buses are different. The inversion detector counts the number of the corresponding bits that are different, and indicates that the instant data bus should be inverted. The inversion detector has a plurality of left shift circuits, each configured to perform a logical left shift of input bits as directed by the states of shift bits, where outputs of the each of the plurality of left shift circuits indicate a number of a subgroup of the corresponding bits that are different.