High-Speed Bus Isolation Circuit for Hazardous Location Signal Integrity

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Solution Overview

Problem

High-speed data transmission in portable electronic devices is limited by form factor constraints and hazardous location requirements, where standard interface designs often compromise signal integrity and safety, particularly in environments with explosive risks, due to added components for overvoltage and overcurrent protection.

Innovation Solution

A high-speed communication interface with an isolation circuit that includes a resistor and capacitor chain for impedance matching and galvanic isolation, protecting against overcurrent and overvoltage failures while maintaining signal integrity, using suppression diodes and inductors to convert capacitance to impedance, thereby enabling safe and efficient data transmission in hazardous environments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If isolation components are added for overvoltage and overcurrent protection in hazardous locations, then safety compliance is improved, but device complexity and component count increase

Engineering Contradiction:
Improvesafety complianceVSAvoidcomponent count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple protection functions (overvoltage protection, overcurrent protection, and galvanic isolation) into a single integrated isolation circuit. The isolation circuit includes a transformer for galvanic isolation, voltage suppression diodes for overvoltage protection, and current-limiting resistors for overcurrent protection, all merged into one circuit block that satisfies hazardous location requirements without requiring separate discrete protection components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The isolation circuit serves multiple functions simultaneously: it provides galvanic isolation between different electrical domains, protects against overvoltage conditions through suppression diodes, limits overcurrent through series resistors, and maintains signal integrity for high-speed data transmission. This multi-functional design reduces the need for separate dedicated components for each protection function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If standard interface designs are used for high-speed data transmission, then data transmission speed is improved, but signal integrity deteriorates in hazardous locations with added protection components

Engineering Contradiction:
Improvedata transmission speedVSAvoidsignal integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The transformer in the isolation circuit acts as an intermediary element that couples the primary and secondary sides magnetically while providing galvanic isolation. This intermediary structure allows high-speed data signals to pass through while blocking harmful electrical transients and maintaining signal integrity. The transformer's magnetic coupling preserves signal fidelity while the galvanic isolation protects against electrical hazards.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent carefully selects and adjusts electrical parameters of the isolation circuit components to maintain signal integrity at high speeds. The transformer operates at frequencies appropriate for high-speed data transmission, the suppression diodes are chosen with low capacitance to minimize signal distortion, and the current-limiting resistors are selected with values that limit fault current while minimizing voltage drop during normal operation. These parameter optimizations enable both high-speed transmission and robust protection.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution ensures optimized signal integrity and compliance with safety standards for high-speed communication in hazardous locations, reducing component count and size while preventing sparks and electrical surges, thus enhancing both safety and performance.

Implementation Method 1

an isolation circuit for the high-speed communication bus. The isolation circuit may include a first terminal and a first resistor. The first terminal may be coupled to the high-speed communication bus and configured to receive a first communication signal from the first high-speed communication processor via the high-speed communication bus. The first resistor may be configured to protect the first terminal from an overcurrent failure condition.

Methodology Applied
Scientific EffectGalvanic isolation: Electrical Resistance

Implementation Method 2

The first resistor may be configured to protect the first terminal from an overcurrent failure condition

Methodology Applied
Scientific EffectElectrical resistance: Electrical Resistance

Implementation Method 3

matching an impedance of the isolation circuit to an impedance associated with the high-speed communication bus

Methodology Applied
Scientific EffectImpedance matching: Electrical Resistance

Implementation Method 4

using suppression diodes and inductors to convert capacitance to impedance

Methodology Applied
Scientific EffectCapacitance to impedance conversion: Capacitance

Implementation Method 5

protect the first terminal from an overvoltage failure condition while maintaining signal integrity of the first communication signal

Methodology Applied
Scientific EffectOvervoltage protection: Electrical Resistance

Data Source

PatentUS20210194721A1System, method, and apparatus providing isolation for a high-speed communication interface with optimized signal integrity
Publication Date: 2021.06.24 MOTOROLA SOLUTIONS INC
  • US20210194721A1 patent drawing
  • US20210194721A1 patent drawing
  • US20210194721A1 patent drawing

AI summary

A portable battery-operated communication device includes a high-speed communication bus, a first high-speed communication processor coupled to the bus and configured for transferring communication signals to a second high-speed communication processor over the bus, and an isolation circuit for the bus with a first terminal coupled to the bus and configured to receive a first communication signal from the first processor via the bus, and a first resistor that is coupled to the first terminal and configured to protect the first terminal from an overcurrent failure condition, in which the isolation circuit is configured to match impendences between the isolation circuit and bus, isolate series inductance associated with the first terminal, protect the first terminal from an overvoltage failure while maintaining signal integrity of the first communication signal, and pass through the first communication signal from the first terminal to a second terminal coupled to the high-speed communication bus.