Bus-line arrangement for gate driver resistance balancing
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Solution Overview
Problem
In thin-film transistor liquid crystal display (TFT LCD) panels, the integrated gate driver-on-array (GOA) structure leads to significant resistance differences between adjacent signal lines, causing undesirable band patterns in the display image due to varying pulse shapes, which affect visual quality.
Innovation Solution
The bus lines are rearranged to minimize the largest resistance difference between adjacent signal-line pairs by altering the order in which clock signals are received, ensuring that the resistance difference in any pair is either R or a controlled value (e.g., 2R, 3R, 4R) rather than the original 5R, thereby reducing the repetitive band pattern effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bus lines are arranged in an orderly fashion to receive clock signals, then the circuit layout is simple and easy to manufacture, but the resistance difference between adjacent signal lines becomes large (5R), causing noticeable band patterns
Solution Approach 1:
The patent applies parameter changes by reordering the assignment of clock signals to bus lines. Instead of assigning clock signals in sequential order (CK1 to B1, CK2 to B2, etc.), the patent uses a specific permutation pattern that distributes the resistance differences more evenly across adjacent signal lines. This changes the electrical parameter distribution (resistance differences) from a large step pattern (R, R, R, R, 5R) to a more uniform pattern where maximum difference is reduced to 2R or 3R, thereby reducing visible band patterns while keeping the physical layout simple
2Object-affected harmful factors
If bus lines are rearranged to minimize resistance differences between adjacent signal lines, then band patterns are reduced, but the bus line arrangement becomes more complex
Solution Approach 1:
The patent resolves this contradiction by finding an optimal parameter arrangement - a specific permutation of clock signal assignments to bus lines. The permutation pattern (such as B1-CK1, B2-CK2, B3-CK4, B4-CK3, B5-CK6, B6-CK5 or similar variations) creates a balanced distribution of resistance differences across all adjacent signal line pairs. This optimal parameter setting achieves the dual goal of minimizing maximum resistance difference (to 2R or 3R instead of 5R) while maintaining a relatively simple and systematic arrangement rule that is easier to implement than arbitrary complex layouts
Data Source
AI summary
A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.