Multi-lane Bus Link Training and Power Management
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Solution Overview
Problem
Current DisplayPort technology is over-designed for 'smart source' paradigms and lacks sufficient processing capabilities for internal consumer electronics components like camera modules, requiring substantial modifications for link training, initialization, and management in 'smart sink' applications.
Innovation Solution
The implementation of a method for training, initializing, and managing a unidirectional sink-driven A/V interface using a multi-lane link, which includes caching link training data for power-efficient operation and transitioning between low power and normal modes, enabling reduced link re-initialization overhead and optimized power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DisplayPort technology is used for internal consumer electronics components, then data transfer capability is improved, but processing capability is insufficient
Solution Approach 1:
The patent introduces a sink device with processing capabilities that acts as an intermediary between the camera module and the application processor. The sink device receives data from the camera module via the DisplayPort interface, performs necessary processing operations, and then forwards the processed data to the application processor, thereby compensating for the insufficient processing capability of the camera module while maintaining high data transfer capability
Solution Approach 2:
The patent divides the system into distinct functional segments: the camera module segment responsible for data generation, the DisplayPort interface segment for high-speed data transfer, the sink device segment for intermediate processing, and the application processor segment for final processing. This segmentation allows each component to be optimized for its specific function while working together in the overall system
2Productivity
If link training protocol is performed over multi-lane unidirectional link, then data transaction capability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic link training where the link training protocol is performed only when necessary (e.g., when transitioning from low power state to active state or when link conditions change), rather than continuously. During active data transmission, the link operates in a steady state without repeated training sequences, significantly reducing power consumption while maintaining data transaction capability
Solution Approach 2:
The patent performs link training in advance when the system transitions to active state, so that the link is already trained and ready for immediate data transmission. This preliminary action avoids the need for repeated training during active operation, reducing overall power consumption while ensuring data transaction capability is available when needed
3Use of energy by moving object
If link training data is cached for power-efficient operation, then power consumption is reduced, but link re-initialization overhead is reduced
Solution Approach 1:
The patent caches link training data in advance during active operation or during the transition to low power state. This cached data is stored in memory and retrieved when transitioning back to active state, eliminating the need for repeated link training and reducing both power consumption and re-initialization time
Solution Approach 2:
The patent creates a copy of the link training data and stores it in cache memory. This copied data can be quickly retrieved and reused when the link needs to be re-initialized, avoiding the time-consuming process of performing the complete link training protocol again while reducing power consumption
Data Source
AI summary
Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.