Centralized Lock Master for Bus Lock and TLB Invalidation
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Solution Overview
Problem
Conventional bus lock and Translation Lookaside Buffer (TLB) invalidation methods in multiprocessor systems are inefficient, particularly in larger systems, as they require complex interconnect topologies and point-to-point communication, leading to performance issues and scalability problems.
Innovation Solution
A centralized lock master and synchronization master manage bus locks and TLB invalidations by broadcasting quiesce and synchronization messages, allowing processors to cease transactions and ensuring atomic operations, thereby simplifying the interconnect fabric and reducing communication overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bus lock solution is used with distributed arbitration at each switch point, then atomic transactions can be enforced, but device complexity increases and scalability deteriorates
Solution Approach 1:
The patent extracts the lock arbitration function from distributed switch points and centralizes it in a dedicated lock master component. The lock master receives lock requests, grants exclusive access to the interconnect fabric, and coordinates lock release, eliminating the need for complex distributed arbitration logic at each switch point while maintaining atomic transaction enforcement.
Solution Approach 2:
The lock master acts as an intermediary between processors seeking atomic transactions and the interconnect fabric. It mediates access by granting exclusive rights to lock holders, managing lock state transitions, and coordinating with TLB synchronization, thereby simplifying the interconnect topology while ensuring reliable atomic operation enforcement.
2Reliability
If point-to-point communication is used for TLB invalidation synchronization, then translation changes can be synchronized, but communication overhead increases and productivity decreases
Solution Approach 1:
The patent merges TLB invalidation synchronization with the bus lock mechanism. The lock master, which already coordinates bus lock operations, also handles TLB synchronization by receiving invalidate requests, broadcasting quiesce messages to all processors, and managing the synchronization sequence. This consolidation eliminates separate point-to-point communication paths and reduces overall communication overhead.
Solution Approach 2:
The lock master is designed with multi-functionality, serving both as the arbiter for atomic transactions and as the synchronization coordinator for TLB invalidations. This universal component handles diverse synchronization scenarios (single processor, multiple processors, nested locks) through a unified message-passing interface, improving productivity by reducing the complexity of dedicated synchronization pathways.
3Reliability
If explicit interrupt handlers are used for TLB invalidation, then translation changes can be synchronized across processors, but loss of time increases
Solution Approach 1:
The patent replaces the software-based interrupt handler mechanism with a hardware-based message-passing system. The lock master sends quiesce requests and synchronization messages directly through hardware interconnect pathways, and processors respond with hardware-generated quiesce granted messages. This substitution eliminates the overhead of context switching, interrupt handler execution, and software bookkeeping, significantly reducing the time required for cross-processor TLB synchronization while maintaining reliability.
Data Source
AI summary
A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.