Bus Master Direct Access for High-Speed SoC Simulation
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Solution Overview
Problem
The increasing complexity of System on a Chip (SoC) bus topology and the need for higher-speed simulations are hindered by the sequential nature of bus access through interconnects, leading to decreased simulation speed, especially when bus slaves like timers or ROM/RAM are involved, which cannot perform operations beyond read/write.
Innovation Solution
A control program and method that allow a bus master to directly access a bus slave if a pointer is held, or access via an interconnect if not, optimizing the bus access route based on the presence of a pointer, thereby enabling high-speed simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bus access is executed sequentially via interconnect APIs between bus master and bus slave, then the bus topology can be maintained and operations can be performed, but the simulation speed decreases in proportion to the number of interconnects
Solution Approach 1:
The bus access path is segmented into two types: direct access paths for simple read/write operations (bypassing interconnects) and indirect access paths through interconnects for complex operations. This segmentation allows high-speed direct access for simple transactions while maintaining the ability to handle complex bus topology operations through the interconnect API path.
Solution Approach 2:
A pointer holding section is introduced as an intermediary mechanism that stores pre-computed access path information. This pointer acts as a mediator that directs bus access either directly to the bus slave or through the interconnect, eliminating the need for sequential API calls through multiple interconnects for simple operations.
2Adaptability or versatility
If bus access is executed via interconnect, then complex bus topology can be supported, but the number of API calls increases and simulation speed decreases
Solution Approach 1:
The bus access mechanism dynamically selects between two paths based on the operation type: direct access for simple read/write operations and interconnect-mediated access for complex operations. This dynamic adaptation allows the system to optimize for speed when possible while maintaining versatility for complex topologies when needed.
Solution Approach 2:
Access path information is prepared in advance and stored in the pointer holding section before actual bus operations occur. This preliminary action of pre-computing and storing access paths eliminates the need for sequential API calls during simulation, significantly improving productivity while maintaining support for complex bus topologies.
3Speed
If direct bus access is implemented using pointer, then simulation speed improves, but the bus configuration becomes different from hardware
Solution Approach 1:
Different access methods are applied to different locations in the bus topology: direct access is used for simple read/write operations to specific bus slaves, while interconnect-mediated access is used for complex operations. This local differentiation allows high-speed direct access where appropriate while maintaining hardware-like behavior for complex operations, preserving overall hardware fidelity.
Data Source
AI summary
A control program capable of properly executing high-speed simulation is provided. The control program according to the present disclosure causes an information processing apparatus to execute a control method, the information processing apparatus including a virtual environment for executing a simulation target program. The virtual environment includes a bus master, an interconnect, and a bus slave connected to the bus master via the interconnect. The control method includes an access processing step of causing the bus master to execute the bus access to the bus slave in a different route depending on whether a pointer for executing the bus access from the bus master to the bus slave is held in a pointer holding section, and an operation executing step of causing the bus slave to execute a predetermined operation when being triggered by the bus access from the bus master.