Serial Bus Master Dummy Bit Transmission
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Solution Overview
Problem
Direct memory access (DMA) controllers face resource burdens when performing DMA transfers over serial communication buses, such as SPI, due to the need to frequently write and read descriptors between system memory and the serial bus master, which can hinder system performance and resource access.
Innovation Solution
Implementing automatic transmission of dummy bits by a serial bus master, where a single DMA descriptor is used to manage data transfers, allowing the serial bus master to initiate and control data exchanges with a slave, reducing the need for frequent descriptor transfers and minimizing system resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent descriptor transfers are performed between system memory and serial bus master, then data transfer completeness is ensured, but system resource burden increases and performance deteriorates
Solution Approach 1:
The system pre-loads dummy bits into an internal buffer before actual data transfer begins. This preliminary action allows the serial bus master to automatically transmit dummy bits without needing to frequently access descriptors in system memory, thereby reducing resource burden while maintaining transfer reliability
Solution Approach 2:
Instead of transferring actual dummy data from system memory during each transfer cycle, the system creates a copy stored in an internal buffer that can be repeatedly used. This copying mechanism eliminates the need for frequent descriptor transfers while ensuring data integrity
2Adaptability or versatility
If multiple DMA descriptors are used for multiple block transfers, then transfer flexibility is improved, but device complexity and resource usage increase
Solution Approach 1:
A single DMA descriptor is designed to handle multiple block transfers by incorporating a counter that tracks the number of transfers remaining. This universal descriptor can be reused for multiple blocks, providing transfer flexibility while eliminating the need to manage multiple separate descriptors, thus reducing device complexity
Solution Approach 2:
The DMA descriptor includes dynamic counter fields that automatically decrement with each transfer block. This dynamic mechanism allows the same descriptor structure to adapt to varying numbers of transfer blocks without requiring manual intervention or multiple static descriptors, balancing flexibility with simplicity
Data Source
AI summary
Various embodiments are disclosed for automatic transmission of dummy bits in a serial bus master. The disclosed embodiments allow a single DMA descriptor to be fetched from memory for the reception of a specified amount of data. Dummy bits can be located or generated in the serial bus master either as a user configurable value or a default value. Logic in the serial bus master initiates a data transfer by writing a count value representing an amount of data to be received to a count register in the serial bus master. The single DMA descriptor is then configured to handle the internal transfer of bits received by the serial bus master from a serial bus slave and the DMA controller is enabled. When data transfer is initiated, the serial bus master starts sending dummy bits to the serial bus slave and receiving data bits from the serial bus slave.