Bus Master Speed Detection via In-Band Test Sequences
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Solution Overview
Problem
Current serial bus protocols, such as I3C, I2C, and SPI, lack a mechanism for the sender to determine the receiver's speed capabilities a priori, leading to suboptimal data transfer speeds as the sender must assume a lowest common clock speed.
Innovation Solution
Incorporating in-band operating frequency determination logic in the master device to generate test sequences at increasing clock rates, allowing it to determine the highest operating speed of the slave device by detecting acknowledgement signals, thereby selecting the safest and fastest operating frequency for communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the sender assumes a lowest common clock speed for data transfers, then compatibility with all receiver types is ensured, but data transfer speed is suboptimal
Solution Approach 1:
The patent applies preliminary action by having the master device perform speed capability detection before actual data transfer operations. The master device sends test sequences at different clock rates and receives feedback about the receiver's maximum operating speed, allowing it to pre-determine the optimal transfer speed for each receiver type.
Solution Approach 2:
The patent implements feedback mechanisms where receivers send acknowledgment signals in response to test sequences transmitted by the master device. This feedback loop allows the master device to determine the receiver's speed capabilities and adjust subsequent data transfers accordingly, resolving the contradiction between compatibility and speed optimization.
2Speed
If test sequences are transmitted at increasing clock rates to determine maximum operating speed, then data transfer speed is optimized, but additional communication overhead is introduced
Solution Approach 1:
The patent applies partial action by transmitting test sequences at selectively determined clock rates rather than exhaustively testing all possible speeds. The master device increments clock rates until acknowledgment signals cease, performing only the necessary tests to determine maximum operating speed without unnecessary overhead.
Solution Approach 2:
The speed detection using test sequences is performed as a preliminary operation before actual data transfer. This one-time initial characterization of receiver capabilities avoids repeated speed negotiation overhead during normal operation, as the master device can then transfer data at the determined optimal speed.
3Speed
If in-band operating frequency determination logic is incorporated in the master device, then data transfer speed is optimized, but device complexity increases
Solution Approach 1:
The master device's existing communication infrastructure is used for dual purposes: normal data transfer and speed capability detection. The same bus interface and signal lines carry both test sequences for speed determination and actual data transfers, eliminating the need for separate dedicated test equipment and reducing overall system complexity.
Solution Approach 2:
The patent merges the speed detection function with the existing master device architecture. The logic for generating test sequences, transmitting them at varying clock rates, and interpreting acknowledgment signals is integrated into the master device's control unit, combining multiple functions into a single unified system rather than adding separate complexity.
Data Source
AI summary
One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.