Bus Node Address Verification via Current Measurement
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Solution Overview
Problem
Existing auto addressing methods in data bus systems, particularly in the automobile industry, fail to reliably detect static errors in bus node address allocation, leading to incorrect address positions and increased production costs due to complex end tests.
Innovation Solution
A method involving a bus master that allocates addresses to bus nodes with current measuring circuits, where each node supplies a current and reports detection results for verification, allowing the bus master to compare expectations and detect errors, thereby ensuring correct address allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If auto addressing methods are used in data bus systems, then address allocation is automated, but static errors in bus node address allocation cannot be reliably detected
Solution Approach 1:
The patent applies preliminary action by performing a verification addressing cycle after the initial auto addressing process. During this verification cycle, the bus master sends addressing currents to verify the correctness of allocated addresses before the bus nodes are put into operation, thereby detecting static errors that would otherwise remain undetected
Solution Approach 2:
The patent implements feedback by having bus nodes send acknowledgment signals back to the bus master during the verification addressing cycle. The bus master receives these acknowledgments and determines whether the address allocation is correct based on the presence or absence of expected acknowledgment signals, creating a closed-loop verification system
2Reliability
If complex production line end tests are performed to detect address allocation errors, then error detection capability is improved, but production costs increase
Solution Approach 1:
The patent applies self-service by enabling the data bus system to automatically verify its own address allocation correctness through the verification addressing cycle. The bus master and bus nodes perform mutual checking using existing addressing current mechanisms, eliminating the need for external complex production line test equipment and reducing production costs
3Reliability
If redundant second addressing cycles are performed for verification, then trustworthiness of addressing is improved, but static errors are still not reliably detected
Solution Approach 1:
The patent performs the verification addressing cycle as a preliminary check before the bus nodes are activated for normal operation. This timing ensures that address allocation errors are detected and corrected before they can cause system malfunctions, while minimizing additional time loss by using the same addressing current mechanism already in place
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability of address verification, detects both intermittent and static errors, and simplifies production end tests by providing a clear determination of bus node positions, ensuring accurate address allocation and reducing production costs.
Implementation Method 1
each bus node comprises a current measuring circuit which is connected to the data bus in series and a current source for supplying current into the data bus
Data Source
AI summary
Disclosed is a method for detecting an erroneous bus node address allocation in data bus systems with auto addressing using an addressing current, such as LIN data bus systems with auto addressing. The method comprises performing auto addressing of the n bus nodes, causing an addressing current to be supplied by a bus node, sensing the data bus current by the bus nodes and determining a bus node-specific bus current measurement value, deciding, whether an addressing current flows through the respective bus node, and determining a bus node-specific addressing current presence value, transmitting the bus node-specific bus current measurement value and/or the bus node-specific addressing current presence value from the bus node to the bus master, forming a supply bus node-specific result vector from the received bus node-specific addressing current presence values, and comparing the supply bus node-specific result vector and a supply bus node-specific expectation vector.