Motor Vehicle Module Bus Node Control With Auto-Addressing
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Solution Overview
Problem
Existing two-wire bus systems for vehicle lighting modules require precise clock generators and complex synchronization, leading to high hardware complexity and potential installation errors, especially in dynamic lighting systems with multiple LEDs or OLEDs.
Innovation Solution
A method for addressing bus nodes using a serial, bidirectional, differential two-wire communication bus that transmits information as a voltage difference between two single-wire buses, allowing auto-addressing and simplified synchronization through differential signaling, reducing the need for precise clock generators and enabling cost-effective UARTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential two-wire bus systems are used for vehicle lighting modules, then transmission speed and robustness are improved, but hardware complexity increases due to precise clock generators and synchronization requirements
Solution Approach 1:
The bus nodes automatically determine their physical position during installation and connection in the vehicle factory and convert this into a logical address without requiring manual preprogramming. This self-addressing mechanism eliminates the need for complex manual configuration and reduces hardware complexity while maintaining reliable communication
Solution Approach 2:
The patent changes the synchronization approach from requiring precise clock generators to using simplified synchronization mechanisms. The bus master and bus nodes synchronize communication without needing highly accurate clock signals, thereby reducing hardware complexity while maintaining signal reliability
2Measurement precision
If precise clock generators are used for synchronization in two-wire bus systems, then transmission accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive precise clock generators with simpler, more cost-effective synchronization mechanisms. The system uses simplified timing approaches that do not require high-precision oscillators, thereby reducing manufacturing costs while maintaining adequate synchronization for reliable data transmission
Solution Approach 2:
The patent changes the clock precision requirement from high-precision to simplified synchronization. By modifying the synchronization parameters and using the bus master's timing signals, the system achieves adequate synchronization without requiring expensive precise clock generators in each bus node
3Reliability
If manual preprogramming of bus node addresses is required, then error reduction is improved, but production logistics and complexity increase
Solution Approach 1:
The bus nodes automatically determine their physical position during installation and connection in the vehicle factory and convert this into a logical address without requiring manual preprogramming. This self-addressing mechanism eliminates the need for complex manual configuration and reduces hardware complexity while maintaining reliable communication
Solution Approach 2:
The system performs address assignment automatically during the installation and connection process in the vehicle factory. The physical position is detected and converted to a logical address as part of the initial setup, eliminating the need for preprogramming and simplifying production logistics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies hardware complexity, reduces installation errors, and enables robust, high-speed data transmission with asynchronous digital interfaces, suitable for vehicle lighting modules like rear and interior lights, using standardized UARTs and simplified clock synchronization.
Implementation Method 1
The information signals are transmitted between the control unit and the participants as a voltage difference between the two bus lines, thereby achieving greater signal reliability, higher transmission speed, and lower susceptibility to interference
Data Source
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AI summary
The invention relates to a device for controlling bus nodes (BK1 to BKn) with a differential communication bus (DB) and a bus master (ECU), wherein the serial, bidirectional, differential communication bus (DB) comprises a first single-wire bus (DBa) and a second single-wire bus (DBb). Each bus node (BKj) has a differential interface (IFj), an address recognition unit (ADRj), and a bus node address register (BKADRj). The communication bus (DB) can be in at least a first differential logical state (z1) and a second differential logical state (z2). The interface (IFj) is connected to the communication bus (DB) to send and/or receive data. The bus master (ECU) transmits data to be sent as sequences of bits in bitstream packets (frames, BP). The bit stream packets (BP) sent by the bus master (ECU) contain data information (DATA).The data information (DATA) comprises address information (ADRD) and user information (INFO). The address recognition units (ADR1 to ADRn) evaluate the address information (ADRD) of the bit stream packets (BP) and only allow the bus node (BKj) to use the contained user information (INFO) if the content of the address information (ADRD) corresponds to the content of the bus node address register (BKADRj). The bus node (BKj) has means to perform an auto-addressing procedure to populate the bus node address register (BAKDRj) with a logical bus node address that corresponds to the physical position of this bus node (BKj) among the n bus nodes (BK1 to BKn) within the differential two-wire communication bus (DB). Clock synchronization information is also transmitted. The addressing mode is initiated by a signal from the bus master (ECU).