Bus Node Shunt Bypass Switch for LIN Addressing
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Solution Overview
Problem
Existing serial data bus systems face limitations in addressing a large number of bus nodes due to high electrical resistance of bus shunts, limited current capacity, and inefficiencies in auto-addressing processes, which hinder the ability to maximize addressing current while preventing bus master overload and ensuring robustness.
Innovation Solution
The method involves using a bridging switch to bypass current measuring devices after address assignment, allowing only addressed bus nodes to participate in normal operation, and gradually increasing addressing currents to manage bus current levels, ensuring that only the last unaddressed node accepts its address within the maximum permissible current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the resistance of the bus shunt is reduced to minimize losses and achieve LIN bus conformity, then the electrical resistance decreases, but the voltage level across the bus shunt during addressing decreases, reducing the ability to detect addressing current levels
Solution Approach 1:
The patent applies dynamics by switching the bus shunt between two operational states: during addressing phase, the shunt remains active to enable current level detection for auto-addressing; during normal operation, the shunt is bypassed to minimize resistance and power losses. This dynamic switching resolves the contradiction by adapting the shunt's presence based on operational requirements.
Solution Approach 2:
The patent implements preliminary action by pre-configuring a bypass switch that can be activated after address assignment. This allows the system to prepare for low-resistance operation in advance, switching the bypass into position once addressing is complete, thereby minimizing losses during the extended operational phase while maintaining detection capability during the initial addressing phase.
2Quantity of substance
If as many addressing bus nodes as possible are addressed, then the number of addressable nodes increases, but the total current drawn by the bus master increases, potentially exceeding the 40mA limit
Solution Approach 1:
The patent applies preliminary action by implementing a two-phase process: first, the bus master determines the total current capability and calculates the maximum number of addressable nodes; second, addresses are assigned sequentially while monitoring current consumption. This preliminary calculation and sequential assignment prevents exceeding the 40mA limit while maximizing the number of addressed nodes.
Solution Approach 2:
The patent implements feedback by continuously monitoring the total current drawn during the addressing process. The bus master measures the current contribution of each addressed node and uses this feedback to determine when to stop addressing additional nodes, ensuring the total current remains within the 40mA limit while maximizing the number of addressed nodes.
3Measurement precision
If the addressing current is increased to maximize the voltage level across the bus shunt, then the detection capability improves, but the bus master may become overloaded
Solution Approach 1:
The patent applies dynamics by adjusting the addressing current level based on the number of addressed nodes. The bus master calculates an appropriate addressing current that provides sufficient voltage level for detection while keeping the total current within safe limits. This dynamic current adjustment resolves the contradiction by optimizing detection capability without causing overload.
4Adaptability or versatility
If a bus shunt resistor is inserted in each addressing bus node to enable auto-addressing, then the addressing capability is enabled, but the EMC behavior deteriorates compared to standard-compliant LIN bus nodes
Solution Approach 1:
The patent applies segmentation by separating the auto-addressing function from the normal operation function. The bus shunt and addressing current source are activated only during the addressing phase to enable auto-addressing capability. During normal operation, these components are deactivated or bypassed, so they do not continuously degrade EMC behavior. This temporal segmentation resolves the contradiction between enabling addressing capability and maintaining EMC performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces bus shunt resistance, enables addressing of more nodes, maintains robustness, and prevents bus master overload by efficiently managing addressing currents, thereby improving the auto-addressing process and reducing EMC issues.
Implementation Method 1
the resistance to a minimum in normal operation after auto-addressing has been carried out
Data Source
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AI summary
The invention relates to a bus node capable of carrying out a method according to the invention for assigning bus addresses to bus nodes of a serial data bus system. The method for assigning bus addresses to bus nodes of a serial data bus system is carried out using bus shunt resistors (R2) in the individual bus nodes (SL1, SL2, SL3) of the data bus system during an assignment period. After carrying out the method for assigning bus addresses to the bus nodes of the serial data bus system during the assignment period, an operating period follows. The bus node includes such a bus shunt resistor (R2). The bus node is characterized by a bus shunt bypass switch (S4) which is open before a bus address is assigned to the bus node during the assignment period and which is closed after a bus address is assigned to the bus node during the assignment period and which remains closed during the operating period.