Bus Protocol Translation Controller Using Lookup Table
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Solution Overview
Problem
Conventional computing systems require complex and power-consuming interface logic to translate transaction requests between different bus protocols, leading to increased die size and design complexity, which becomes a challenge when new requesting units or transaction types are added.
Innovation Solution
A bus protocol translation controller employs a mapping table structure and a lookup table to translate transaction requests and responses between different bus protocols, allowing for dynamic reconfiguration without requiring changes to the integrated circuit die layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hardcoded translation schemes are used for each requesting unit, then translation accuracy is improved, but die size increases and design complexity increases
Solution Approach 1:
The patent implements a universal translation apparatus that can translate transactions between multiple different bus protocols (e.g., CXL, PCI, PCIe, NVLink, HPI, AXI, AHB, APB) using a single set of configurable logic elements. The translation logic is controlled by protocol identification fields and configurable parameters that allow the same hardware structure to adapt to different protocol combinations, eliminating the need for separate hardcoded translation paths for each requesting unit while maintaining accurate protocol translation.
Solution Approach 2:
The translation apparatus uses configurable translation logic that can be dynamically adjusted through protocol identification fields and control parameters. The system identifies the source and target protocols and dynamically selects the appropriate translation parameters and data path configurations, allowing the hardware to adapt its behavior based on the specific protocol combination being used rather than requiring static hardcoded paths for each scenario.
2Reliability
If hardcoded translation schemes are used for each requesting unit, then translation functionality is improved, but power consumption increases
Solution Approach 1:
The translation apparatus consolidates multiple protocol translation functions into a single shared hardware structure that can be dynamically configured. By using universal translation logic controlled by protocol identification fields and configurable parameters, the system activates only the specific translation paths needed for the current transaction type, avoiding the continuous power consumption that would result from maintaining multiple separate hardcoded translation schemes simultaneously active.
3Adaptability or versatility
If new requesting units are added to the system, then system capability is improved, but new die designs are required
Solution Approach 1:
The translation apparatus is designed with configurable parameters and protocol identification fields that can be programmed to recognize and translate transactions from new bus protocols without requiring physical die changes. When a new requesting unit or protocol is added, the system can be reconfigured through software or firmware to add the appropriate protocol identification rules and translation parameters, allowing the same hardware die to support evolving system requirements.
Solution Approach 2:
The system allows new requesting units and protocols to be integrated by changing configurable parameters such as protocol identification field values, translation mapping tables, and control register settings. This parameter-based configuration approach enables the addition of new protocols (e.g., adding support for a new CXL version or a different interconnect protocol) without requiring new die designs, as long as the underlying translation architecture can accommodate the new protocol's transaction structure.
4Measurement precision
If protocol-specific translation logic is implemented for each bus protocol, then translation precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a unified translation apparatus that handles multiple bus protocols (CXL, PCI, PCIe, NVLink, HPI, AXI, AHB, APB) through a single configurable logic structure. The apparatus uses protocol identification fields to determine the source and target protocols, then applies appropriate translation parameters to maintain precise translation without requiring separate dedicated logic paths for each protocol combination. This universal approach reduces device complexity while preserving translation precision through configurable parameter sets.
Data Source
AI summary
An apparatus translates transaction requests using a bus protocol translation lookup table (LUT) that comprises bus protocol translation data. A bus protocol translation controller generates the outgoing translated transaction request by translating the incoming transaction request using the bus protocol translation data from the bus protocol translation LUT. The controller translates a received response from the target unit to a response in a first bus protocol for a corresponding requesting unit. Associated methods are also presented. In some examples, the bus protocol translation data corresponds to each of a plurality of requesting units for translating between an incoming transaction request sent via a first bus protocol to an outgoing translated transaction request sent via a second bus protocol for the at least one target unit.