Bus Reconfiguration via Independent Switch Segmentation

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Solution Overview

Problem

Conventional reconfigurable architectures face inefficiencies in configuration and reconfiguration speed due to synchronization dependencies between data processing modules and bus systems, requiring complex hardware to manage IDs and ensure proper interconnection.

Innovation Solution

Implementing double bus switches and additional logic within objects to allow independent configuration and connection management, reducing hardware complexity and enabling faster reconfiguration by allowing objects to connect automatically to corresponding data sources and transmitters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional synchronization dependencies are used between data processing modules and bus systems, then proper interconnection is ensured, but reconfiguration speed decreases and hardware complexity increases

Engineering Contradiction:
Improveproper interconnectionVSAvoidreconfiguration speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-configuring multiple bus switches and interconnection paths before reconfiguration is needed. Objects prepare connection information in advance, allowing rapid switching during reconfiguration without waiting for complex synchronization dependencies to resolve.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the bus system into multiple independent bus segments with individual switches. This segmentation allows independent configuration of each segment, eliminating the need for global synchronization and enabling parallel reconfiguration operations that significantly improve reconfiguration speed.

Inventive Principle:
Principle #1Segmentation

2Reliability

If complex hardware is used to manage IDs and ensure proper interconnection, then synchronization is maintained, but device complexity increases

Engineering Contradiction:
ImprovesynchronizationVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the synchronization management function from complex centralized hardware control and implements it through simpler distributed mechanisms. Each object manages its own connections locally, eliminating the need for complex centralized ID management hardware while maintaining synchronization through peer-to-peer coordination.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements self-service by enabling each object to autonomously manage its own interconnections and synchronization. Objects automatically establish and maintain their own connection states without requiring complex external control hardware, reducing overall device complexity while preserving reliable synchronization through local autonomy.

Inventive Principle:
Principle #25Self-service

3Productivity

If independent configuration is allowed for objects, then reconfiguration time decreases, but connection management complexity increases

Engineering Contradiction:
Improvereconfiguration timeVSAvoidconnection management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements universality by providing a standardized set of connection management interfaces and protocols that all objects use uniformly. This standardization allows independent configuration of each object while simplifying connection management through common mechanisms, avoiding the need for complex object-specific management logic.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8127061B2Bus systems and reconfiguration methods
Publication Date: 2012.02.28 PACT XPP TECH
  • US8127061B2 patent drawing
  • US8127061B2 patent drawing
  • US8127061B2 patent drawing

AI summary

A processor chip includes data processing elements that each has dedicated to it a respective switch for dynamically establishing an interconnection between the data processing elements conditional upon verification of a validity of the interconnection, which verification is automatically performed by at least one of the data processing elements to be interconnected.