Semiconductor Bus Relay Device Priority Conversion
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Solution Overview
Problem
Existing bus systems in semiconductor integrated circuits face challenges in maintaining high transmission performance and flexibility due to variations in transmission delays and process performance across different nodes and buses, leading to inefficiencies in combining semiconductor modules.
Innovation Solution
A bus system with a relay device that includes a buffer for storing data, a packet generator for attaching priority information, a priority converter for adjusting packet priorities based on transmission delays, and a sending controller for managing packet transmission in descending order of priority, allowing for flexible settings and optimal transmission performance across varying chip combinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If buses are connected via routers with different quality requirements sharing the same bus, then the number of buses is reduced, but transmission delays increase significantly
Solution Approach 1:
The patent segments traffic flows into different classes (first class with small delay, second class with large delay) and assigns them to different transmission paths. High-priority traffic bypasses routers connected by low-speed links, while low-priority traffic uses the standard routed path, thereby reducing overall transmission delay while maintaining bus sharing benefits
Solution Approach 2:
The patent introduces a traffic flow classification mechanism as an intermediary that directs different types of traffic through different paths. The classification unit acts as a mediator between the router and the transmission medium, enabling selective routing that optimizes delay performance for time-sensitive traffic
2Adaptability or versatility
If settings are done for each module or each master to achieve flexible bus system, then transmission performance is optimized, but device complexity increases
Solution Approach 1:
The patent implements a universal traffic classification mechanism that can be applied across different modules and masters without requiring individual customization. The same classification units and transmission path selection logic are used throughout the system, providing flexible performance optimization through a standardized approach rather than module-specific configurations
3Adaptability or versatility
If low-speed buses are used to connect chips together, then compatibility is improved, but transmission delays become significant
Solution Approach 1:
The patent segments traffic based on delay sensitivity and routes time-critical traffic through high-speed direct paths that bypass low-speed inter-chip links. Non-critical traffic continues to use the low-speed compatible buses, thereby achieving both compatibility and high performance for sensitive applications
Data Source
AI summary
A bus system (100) for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device (250) arranged on the bus. The bus system (100) includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (202), information specifying a priority of transmission. The relay device (250) converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device (250) stores packets in a buffer (252) based on the priority.