Device Management Bus Reset via FRU Memory Indicator
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Solution Overview
Problem
In Information Handling Systems (IHSs), the unavailability of a bus connecting components can lead to complete communication disruption, and restarting components to resume bus communications may result in downtime, which is undesirable in scenarios where service continuity is critical.
Innovation Solution
A system and method for managing a device management bus that includes a remote access controller to detect an inoperable state, determine if Field Replaceable Unit (FRU) memory is accessible, write a reset indicator, and monitor for a reset notification, allowing for bus controller reset and error message transmission without requiring component restarts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bus communications are resumed by restarting the components, then bus communications are restored, but the components and potentially the IHS become inoperable causing downtime
Solution Approach 1:
The patent segments the reset operation from the bus controller by writing a reset indicator to FRU memory instead of directly resetting the bus controller. This allows the management bus to remain operational while the reset condition is prepared, resolving the contradiction by enabling bus availability while preparing for component restoration.
Solution Approach 2:
The system performs preliminary action by writing the reset indicator to FRU memory before actually resetting the bus controller. This advance preparation allows the bus to remain functional during the indicator writing phase, and the actual reset can be executed at a convenient time without causing immediate downtime.
2Reliability
If sideband management buses are used for monitoring components, then component monitoring is enabled, but restarting monitored components to restart the bus results in service downtime
Solution Approach 1:
The FRU memory acts as an intermediary between the management bus and the bus controller reset operation. By using the FRU memory as a communication medium to pass the reset indicator, the system can monitor and control the bus without requiring immediate component restart, thus maintaining service continuity while enabling component monitoring.
Solution Approach 2:
The bus controller is designed to automatically detect the reset indicator in FRU memory and self-reset without external intervention. This self-service mechanism allows the bus to remain operational for monitoring purposes while the controller can be reset on-demand without requiring manual intervention or causing service downtime.
3Reliability
If bus communications are completely disabled when a bus becomes unavailable, then communication failures are prevented, but all communications between components are disabled
Solution Approach 1:
Instead of completely disabling bus communications when a failure is detected, the system applies partial action by allowing the bus to remain operational while writing the reset indicator to FRU memory. This selective approach prevents communication failures from propagating while maintaining necessary communication pathways for monitoring and recovery operations.
Data Source
AI summary
Embodiments are described for operating a device management bus coupled to a remote access controller and a managed device. The remote access controller detects an inoperable state of the bus and determines a FRU (Field Replaceable Unit) memory is accessible on the managed device. A predefined reset indicator is written to the FRU memory. The managed device monitors for the reset indicator being written to a specified location in FRU memory. Upon detecting the reset indicator in FRU memory, the managed device resets a bus controller coupled to the device management bus and transmits a reset notification on the device management bus. The remote access controller may include an I2C shim that controls access to an I2C multiplexer utilized for transmitting I2C commands from a service processor and an I2C coprocessor, preventing certain inoperable bus states due to concurrent operation of the I2C multiplexer by the I2C coprocessor and the service processor.