Bus Routing with Regular Buffer Arrays
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Solution Overview
Problem
In integrated circuits, the increased number of function blocks and operating speeds lead to challenges in maintaining signal integrity and efficiency in bus routing, as individual connection routing and buffer placement can result in increased jitter and wastage of routing resources.
Innovation Solution
A method for routing a bus in an integrated circuit that involves extracting bus information, generating and placing buffer arrays regularly arranged based on physical requirements, and connecting them to form interconnections, thereby reducing crosstalk and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If individual connection routing is used for bus connections, then routing flexibility is improved, but signal integrity deteriorates due to increased jitter and crosstalk
Solution Approach 1:
The bus routing is segmented into multiple buffer arrays that are regularly spaced along the bus path. Each buffer array processes signals independently, allowing the bus to be divided into manageable segments that maintain signal integrity while preserving routing flexibility through automated placement algorithms.
Solution Approach 2:
Buffer arrays are strategically placed at specific locations along the bus route based on local signal integrity requirements. The regular spacing ensures that areas with higher crosstalk risk or longer transmission distances receive appropriate buffering, while maintaining overall routing adaptability.
2Reliability
If more buffers are added to maintain signal integrity, then signal quality is improved, but routing resource usage deteriorates due to wastage
Solution Approach 1:
The buffer arrays are pre-configured with regular spacing based on extracted bus information and physical requirements. This preliminary arrangement optimizes buffer placement before actual routing, ensuring that buffers are placed only where needed to maintain signal quality without excessive resource consumption.
Solution Approach 2:
The spacing between buffer arrays is optimized based on bus-specific parameters such as length, signal frequency, and crosstalk characteristics. By adjusting the buffer spacing parameter according to actual bus requirements, the system maintains signal quality while minimizing the number of buffers needed, thus reducing routing resource wastage.
3Productivity
If buffer spacing is increased to reduce resource usage, then routing resource efficiency is improved, but signal integrity deteriorates due to increased jitter
Solution Approach 1:
The buffer spacing is dynamically optimized based on extracted bus information including physical requirements and signal characteristics. The system adjusts buffer spacing to be regular and consistent for each bus, balancing resource efficiency with signal integrity requirements through automated calculation and placement.
Data Source
AI summary
Program procedures executed to rout a bus, via a processing unit, include a bus information extractor configured to extract bus information including physical requirements for the bus, from input data, a buffer array generator configured to generate a buffer array in which buffers included in the bus are regularly arranged based on the bus information, a buffer array placer configured to place at least one buffer array in the layout of the integrated circuit based on the bus information, and a wiring procedure configured to generate interconnections connected to buffers included in the at least one buffer array based on the bus information.