Bandwidth Allocation in Packetized Bus via Segmentation and Interleaving
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Solution Overview
Problem
In modern network interface controller (NIC) devices with multiple DMA channels connected over a packetized bus, the distribution of network packet sizes leads to uneven CPU bus bandwidth allocation, resulting in computational inefficiencies and disparate resource distribution among applications with different packet size characteristics.
Innovation Solution
A traffic management device, such as an application delivery controller, segments network packets from multiple DMA channels into smaller constituent CPU bus packets and interleaves them for transmission across a packetized CPU bus, ensuring each DMA channel receives a fair share of bandwidth independent of packet sizes, using techniques like segmentation and reassembly (SAR) into HyperTransport or PCI Express packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If network packets are transmitted directly over the CPU bus without segmentation, then transmission simplicity is maintained, but bandwidth allocation becomes uneven and computational efficiency deteriorates
Solution Approach 1:
The patent segments network packets into smaller fixed-size CPU bus packets (e.g., 64-byte HyperTransport packets) before transmission. This segmentation enables fair bandwidth allocation by ensuring each DMA channel transmits packets of uniform size, preventing any single channel from monopolizing the bus with large variable-length packets. The segmentation process is performed by the network interface controller's packetizer, which divides incoming network packets into multiple smaller constituent packets for orderly bus transmission.
2Productivity
If packets from different DMA channels are transmitted in sequential order, then transmission order is simple to manage, but bandwidth fairness deteriorates as channels with large packets capture more bus time
Solution Approach 1:
The patent implements periodic interleaving of packets from multiple DMA channels, where packets are transmitted in a round-robin fashion across channels. This periodic scheduling ensures that each DMA channel receives equitable bus access regardless of packet size variations. The system alternates between channels in fixed intervals, guaranteeing that channels handling small packets do not wait excessively behind channels with large packets, thus achieving fair bandwidth distribution.
3Productivity
If variable-length network packets are transmitted directly, then packet processing is simpler, but resource distribution becomes disparate and computational efficiency is reduced
Solution Approach 1:
The patent changes the packet size parameter from variable (network packet sizes) to fixed (standardized CPU bus packet sizes). By converting variable-length network packets into fixed-size bus packets through segmentation, the system achieves more predictable bus transmission timing and fairer bandwidth allocation. This parameter transformation allows the bus arbitration logic to operate on uniform packet units, improving computational efficiency and resource distribution while the segmentation overhead is managed by dedicated hardware logic.
Data Source
AI summary
A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.