Serializer Deserializer Mechanism for AMBA Bus Pin Reduction
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Solution Overview
Problem
The complexity and cost of System-on-a-Chip (SoC) designs increase exponentially due to the high number of communication lines required for AMBA bus interfaces, exceeding the limit of available I/O pins, making it impractical for systems with multiple masters and slaves.
Innovation Solution
The implementation of serializers and deserializers reduces the number of communication lines needed by serializing parallel bus information for transmission over a communication bus, inserting wait cycles during serialization and deserialization, thereby reducing the complexity and cost of inter-chip connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard AMBA bus interfaces are used for inter-chip communication, then communication capability between masters and slaves is maintained, but the number of I/O pins required increases exponentially
Solution Approach 1:
The patent transforms the parallel bus interface into a serial communication interface by adding serialization/deserialization functionality. This dimensional change from parallel to serial reduces the number of physical connection lines required from over 100 to just 3-4 lines, while maintaining the same communication capability between AMBA bus masters and slaves across chip boundaries
Solution Approach 2:
The patent introduces serializer and deserializer components as intermediary devices between the AMBA bus interface and the physical communication medium. These intermediaries convert parallel bus signals into serial signals for transmission, eliminating the need for direct parallel connections and reducing I/O pin requirements
2Adaptability or versatility
If the number of masters and slaves is increased in the system, then system functionality and performance are improved, but the number of communication lines required increases exponentially
Solution Approach 1:
The patent creates a universal serial interface that can accommodate any number of AMBA bus masters and slaves without increasing the number of physical communication lines. The serialization mechanism allows multiple devices to share the same serial bus through time-division multiplexing, making the interface scalable and adaptable to systems with varying numbers of masters and slaves
3Speed
If parallel bus information is transmitted directly without serialization, then transmission speed is maintained, but the number of I/O pins required becomes impractical
Solution Approach 1:
The patent accepts a reduction in parallel transmission speed in exchange for dramatically reducing the number of I/O pins from over 100 to just 3-4 lines. The serialization process converts wide parallel buses into narrow serial streams, trading bandwidth for pin count, which makes the system practically implementable while maintaining adequate communication performance
Data Source
AI summary
Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization.