Bus Slave Addressing by Enable-Signal Relay Sequence
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Solution Overview
Problem
Existing master-slave bus systems face challenges in flexible and efficient address assignment, as current methods are either predetermined, complex, or require manual parameterization, especially when dealing with multiple slaves that are far apart, leading to high costs and complexity.
Innovation Solution
A slave unit for a master-slave bus system with a bus interface, control inputs/outputs, and an address memory that uses a broadcast address and allocation address to enable flexible address allocation, allowing units to be assigned unique addresses in the sequence of their cabling, with an enable signal relayed between units to manage allocation mode, and separate circuitry for input and output processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual parameterization is used to assign addresses to slave units, then unique addresses can be assigned, but the process is time-consuming and costly
Solution Approach 1:
The slave units automatically assign addresses to themselves using the enable signal mechanism. When a slave unit receives an enable signal, it automatically enters allocation mode, generates its own address, and transitions to operating mode without external intervention, eliminating manual parameterization time
Solution Approach 2:
The system pre-configures slave units with allocation mode capability and enable signal reception ability during manufacturing. This preliminary preparation allows rapid automatic address assignment during deployment without time-consuming manual configuration
2Ease of operation
If control lines are looped into all slaves for address assignment, then addressing can be controlled, but the system complexity increases
Solution Approach 1:
The invention extracts the address assignment control function from a centralized control line system and distributes it to individual slave units through the enable signal mechanism. Each slave unit independently responds to enable signals and manages its own address allocation, eliminating the need for complex looped control lines
Solution Approach 2:
The address assignment process is segmented into independent slave unit operations. Each slave unit autonomously handles address assignment when receiving an enable signal, breaking down the complex centralized control into simple, independent unit-level operations
3Ease of manufacture
If incremental address assignment is used in series connection, then addresses follow a fixed pattern, but flexible address assignment is not possible
Solution Approach 1:
The address assignment system transitions from a static incremental pattern to a dynamic selection process. Slave units can choose from multiple predefined address patterns (first pattern with addresses 1-N, second pattern with addresses N+1-2N) based on system configuration, enabling flexible address assignment while maintaining manufacturing simplicity
Solution Approach 2:
The system changes the address parameter by allowing slave units to select between different address patterns. This parameter change enables the same hardware to support both incremental assignment and arbitrary address assignment by simply changing which pattern is activated
4Ease of operation
If all slaves must be connected by control line for addressing, then addressing procedure can be controlled, but slaves far apart become problematic
Solution Approach 1:
The enable signal acts as an intermediary that can be transmitted through the existing bus system infrastructure without requiring dedicated control lines between all slaves. This allows address assignment control even when slaves are geographically dispersed, as the enable signal can be routed through the bus network
Data Source
AI summary
The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.