Processor Bus Switch Failure Recovery via Dynamic Routing
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Solution Overview
Problem
Multi-processor systems face downtime and performance issues due to inoperable communication links or bus switches, as existing systems require manual intervention or prolonged downtime for diagnosis and repair when a link fails.
Innovation Solution
Implementing a communication network with multiple bus switches and processors that detect inoperable links, send notification messages, and dynamically update routing tables to reroute data through alternate paths, allowing the system to continue operating until a replacement is available.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a link between processor and bus switch fails, then communication is interrupted, but system downtime increases
Solution Approach 1:
The system performs preliminary actions by detecting link failures through timeout mechanisms and sending notification messages before complete communication collapse occurs. The routing information is proactively updated to exclude failed links, preventing further communication attempts through inoperable paths and reducing overall downtime.
Solution Approach 2:
The routing information in registers is made dynamic and可更新 (updatable). When a link failure is detected, the system dynamically updates the routing tables to reflect current link status, allowing the communication network to adapt its path selection in real-time based on operational conditions rather than using static routing.
2Measurement precision
If manual intervention is required for link failure diagnosis, then repair accuracy improves, but system availability decreases
Solution Approach 1:
The system performs self-service by automatically detecting link failures through timeout detection, sending notification messages to other processors, and updating routing information without requiring manual intervention. This autonomous failure management maintains system availability while ensuring accurate failure detection through programmed diagnostic routines.
Solution Approach 2:
The system implements feedback mechanisms where processors monitor communication links and automatically generate notification messages when failures are detected. This closed-loop feedback system continuously monitors link health and triggers appropriate responses, eliminating the need for manual diagnosis while maintaining accurate failure detection.
3Ease of operation
If routing information is not updated, then message routing simplicity is maintained, but communication efficiency through failed links increases
Solution Approach 1:
Routing information is made dynamic through automatic updates triggered by failure detection. The system balances operational simplicity with efficiency by using a straightforward update mechanism that modifies routing tables only when necessary, maintaining ease of operation while preventing communication attempts through failed links.
4Device complexity
If alternate paths are not used, then system complexity is reduced, but fault tolerance decreases
Solution Approach 1:
Multiple bus switches and communication links are configured with universal routing capabilities, where each processor can communicate through any available link. This multi-functionality allows the system to use alternate paths when failures occur without requiring complex dedicated backup configurations, achieving fault tolerance with moderate complexity.
Data Source
AI summary
A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.