Bus Switching Activity Minimization via Synchronized Sorting Patterns
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Solution Overview
Problem
Current methods for reducing bus switching activity on wide buses are inefficient, particularly due to the need for multiple additional lines for transmitting sorting patterns, which increases electrical energy absorption and switching activity.
Innovation Solution
The use of two functionally identical finite state machines at the transmission and reception ends, synchronized by a single clock signal, allows for the transmission of sorting patterns on a single line, reducing additional switching activity by signaling internal state coincidence through a single switching event.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sorting patterns are transmitted using multiple additional lines, then data can be properly recovered at the reception end, but the bus switching activity increases and electrical energy absorption increases
Solution Approach 1:
The patent merges the transmission of sorting pattern information into a single line by combining the states of multiple finite state machines. Instead of using separate lines for each sorting pattern bit, the invention combines all sorting pattern information into one synchronized signal line, reducing the number of active lines from multiple to just one while maintaining complete data transmission capability.
Solution Approach 2:
The single transmission line serves multiple functions: it carries synchronization signals, transmits sorting pattern information, and enables coordination between transmission and reception ends. The finite state machines at both ends use the same single line for bidirectional communication purposes, making the line universal rather than dedicated to a single function.
2Loss of information
If multiple additional lines are used for transmitting sorting patterns, then sorting pattern information can be transmitted completely, but the number of lines increases and device complexity increases
Solution Approach 1:
The patent merges the transmission of sorting pattern information into a single line by combining the states of multiple finite state machines. Instead of using separate lines for each sorting pattern bit, the invention combines all sorting pattern information into one synchronized signal line, reducing the number of active lines from multiple to just one while maintaining complete data transmission capability.
Solution Approach 2:
The invention uses identical copies of finite state machines at both the transmission and reception ends. These functionally identical FSMs process the same sorting pattern information locally, eliminating the need to transmit every detail of the sorting pattern. The reception end FSM is a copy that can independently determine the sorting pattern from the synchronized signal.
3Reliability
If a synchronization pulse is transmitted to signal internal state coincidence, then the sorting pattern can be transmitted, but double switching edges occur causing increased switching activity
Solution Approach 1:
Instead of using a positive synchronization pulse that transitions from low to high and back (causing double switching), the invention inverts the approach by using a complemented synchronization signal. The signal transitions only once from high to low or vice versa, eliminating the double switching edge problem while maintaining synchronization accuracy. This inversion of the pulse generation approach reduces unnecessary switching activity.
Data Source
AI summary
Described herein is a method for transmitting data on a bus with minimization of the bus switching activity, comprising the steps of converting the datum to be transmitted from its own original format to a transmission format that minimizes the switching activity on the bus, said conversion consisting in swapping the position of one or more bits of the datum to be transmitted, the swapping being performable according to a plurality of different variants, each of which is identified by a respective sorting pattern, and selecting, between the various sorting patterns, an optimal sorting pattern that minimizes the bus switching activity upon transmission on the bus of the datum generated using said optimal sorting pattern.


